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回復 #1 option318 的帖子
回復 #1 option318 的帖子! s! W X: z# B$ q- h4 p7 c2 d
(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一+ d' I- l' J/ ^
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
2 a3 g2 N% w$ k$ Z1 q pll ,且亦有unstability issue& _# Y% `8 e/ e5 H) y; g, H# f0 X4 m
(see Charge-pump phase lock loops paper by Gardner
& U$ _" T$ o3 r8 j# ]6 lIEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
" h3 \% N% N" a% A" ~' E' O(2) loop BW is related to jitter (or phase noise) ,and locking time) F! P* G" b5 g k
so you have to consider loop BW from jitter & locking time spec
) ^+ N9 K* L0 {1 Q/ |- T M(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq- z5 Z! b; U; u) H4 a+ P6 ^
(4) In my opinion ,gain margin is not considered in pll design |
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