在鎖相迴路中如何決定迴路頻寬K呢？

option318

　如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17

kmchen3089

回復 #1 option318 的帖子
9 U: g" |& V% E/ G(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
* q+ }! r# M( K. I pll ,且亦有unstability issue
(see Charge-pump phase lock loops paper by Gardner
IEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
$ s' _) S* w' A4 r(2) loop BW is related to jitter (or phase noise) ,and locking time
so you have to consider loop BW  from jitter & locking time  spec
(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
: ?6 N2 p. M5 C4 B  S% Y(4) In my opinion ,gain margin is not considered in pll design

jasonxilion

gain margin is not considered in pll design？
9 Z* L5 v3 w. @! h( |! Ni don't think so.
isn't it dealt with the stability?

賴永諭

書上都有講哩...加油看看先....
) q* w' m( c* m* O; _8 X. i應該不難找到哩...