大家好，我是新成員，問一個小問題

kyopc

首先，感謝各位撥冗來看我這帖子
7 i; }. C" A' {) e5 h6 ^這個問題算不上是設計，是一個小小的問題
我現在有一個CPU的source code,
) f3 G8 j1 I4 O( O" Jmemory的部份是有一個interface來接收FPGA晶片外部的SRAM資料
/ ^: t  f; L/ s% b5 R4 b% b$ tmemory資料寬度32bit的

" D( V+ \) R" R& `2 Y$ j3 l: T要把他download到我的板子上
但是我的板子上的SRAM只有16bit
請問我要怎麼改寫裡面的VHDL code來符合
& K% `2 \8 p8 t2 }( D
可能對板上的高手來說，這是基本問題
- y& f  ]/ U8 m( M9 z' Q但是我本身不是VLSI設計背景的人
. k+ ]4 M# {4 E8 ]8 D8 f老闆硬要我搞出來 >_<

希望大家不吝給我一點提示,謝謝大家

tommywgt

就算是32BITS CPU也允許16BITS的存取才對, 在這情況下, 什麼都不用修改的, 只需要修改軟體的程式
" \4 M/ ]0 s8 D" H  x
如果一定要做到軟體都不用改的話, 影響的範圍比較大, 你可能需要:
1) SRAM工作於CPU的兩倍頻率
# {" k. f/ U& e, m2) 利用類似BE信號 (BYTE ENABLE)來控制SRAM的存取
3) 如果SRAM速度跟不上CPU, 而且又不想降頻的話, CPU要能支援類似BUSY的控制信號
差不多如此吧, 還有其他我漏掉的嗎???

jason_lin

沒錯,就版主的方式,不然就設計一個FIFO SRAM Controler,丟到fifo裡,讓他自己丟到sram,
如果完全不會寫hdl,那你去網路上收尋,應該有人寫好的吧!
不然Xilinx有提供memory的參考設計,有含HDL code,如下列網址:
http://www.xilinx.com/products/design_resources/mem_corner/
# _: M4 {6 O& u! }你找找,Xilinx的參考設計編號都是XAPP***.pdf,裡面有一個Design file的網址,就是下載soure code的地方^__^

kyopc

感謝兩位前輩的指導
由於工作需求，我的程式是沒辦法改的
換句話說，我必需修改我的硬體
/ [; H9 Q* }/ U1 C& `
. R# B; f4 X0 I8 F3 F2 T  N我會先試試看jason大大的方法，結果再回報給大家
提供經驗給大家
謝謝

tommywgt

Xilinx的XAPP好多, jason_lin有意願整理歸類一下, 發個文跟大伙介紹一下嗎?
* t# l! w" }1 {2 M就以Xilinx的Vertical Segment分類來整理如何?
$ n7 w3 t9 i0 w7 D另外並不是所有的XAPP都有source code的, 可能也要說明一下, 大伙才能更清楚.
! M8 O, g$ J4 ^$ I
先謝囉!

jason_lin

我整理了一些而已ㄝ,如下:
+ A% x" i/ O/ S* _: f; c% ~1 YFPGA
XAPP058        Xilinx In-System Programming Using an Embedded Microcontroller&nbsp;
. K$ h  q" q; a/ D6 {' x' wXAPP195        Implementing Barrel Shifters Using Multipliers&nbsp;
XAPP211        PN Generators Using the SRL Macro&nbsp;
XAPP217        Gold Code Generators in Virtex Devices&nbsp;
+ [, c* Q0 F3 N6 g+ s7 KXAPP220        LFSRs as Functional Blocks in Wireless Applications&nbsp;
XAPP224        Data Recovery&nbsp;
XAPP228        Quad-Port Memories in Virtex Devices &nbsp;
XAPP229        Wider Block Memories&nbsp;
) l- K, T2 m% ^6 x6 K1 Z6 x; K+ gXAPP250        Clock and Data Recovery With Coded Data Streams&nbsp;
) @8 {. o, m& `' q4 W& TXAPP258        FIFOs Using Virtex-II Block RAM&nbsp;
XAPP260        Using Virtex-II Block RAM for High Performance Read/Write CAMs&nbsp;
XAPP261        Data-Width Conversion FIFOs Using the Virtex-II Block RAM Memory&nbsp;
( a" V  y" Q& U1 F9 WXAPP267        Parity Generation and Validation for the Virtex-II Series&nbsp;
8 L' G2 s% C6 q  W, l& pXAPP268        Active Phase Alignment&nbsp;
XAPP284        Matrix Math, Graphics, and Video&nbsp;
XAPP291        Self-Addressing FIFO&nbsp;
XAPP441        Remote FPGA Reconfiguration Using MicroBlaze or PowerPC&nbsp;
XAPP445        Configuring Spartan-3E Xilinx FPGAs with SPI Flash Memories&nbsp;
XAPP454        DDR2 SDRAM Memory Interface for Spartan-3 FPGAs&nbsp;
XAPP462        Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs&nbsp;
XAPP463        Using Block RAM in Spartan-3 Generation FPGAs&nbsp;
XAPP464        Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs&nbsp;
! e# n; z8 b1 @5 y- cXAPP465        Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 Generation FPGAs&nbsp;
$ c  a  E( [9 f: @" [7 A# z5 ]" @$ IXAPP466        Using Dedicated Multiplexers in Spartan-3 Generation FPGAs&nbsp;
XAPP467        Using Embedded Multipliers in Spartan-3 FPGAs&nbsp;
XAPP473        Using the ISE Design Tools for Spartan-3 FPGAs&nbsp;
XAPP474        Using IP Cores in Spartan-3 Generation FPGAs&nbsp;
XAPP475        Using IBIS Models for Spartan-3 FPGAs&nbsp;
$ g$ ]# K! i( W& Z$ f2 aXAPP476        Using BSDL Files for Spartan-3 Generation FPGAs&nbsp;
XAPP477        Embedded Processing and Control Solutions for Spartan-3 Devices&nbsp;
XAPP482        MicroBlaze Platform Flash/PROM Boot Loader and User Data Storage&nbsp;
XAPP483        Multiple-Boot with Platform Flash PROMs &nbsp;
) V0 N4 }! N( g& E: Y1 rXAPP485        1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666 Mbps&nbsp;
" r* W! T% B; B" R, {" XXAPP489        Four- and Six-Layer, High-Speed PCB Design for the Spartan-3E FT256 BGA Package&nbsp;
XAPP491        Inverting LVDS Signals for Efficient PCB Layout in Spartan-3 Generation FPGAs&nbsp;
7 Z) Y  ^/ H9 a( M4 @% n1 m: \7 YXAPP500        J Drive: In-System Programming of IEEE Standard 1532 Devices&nbsp;
XAPP502        Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode&nbsp;
4 t8 T' k* k% v# x& K- _' m6 kXAPP514        Audio/Video Connectivity Solutions for the Broadcast Industry
XAPP529        Connecting Customized IP to the MicroBlaze Soft Processor Using the Fast Simplex Link(FSL)&nbsp;
XAPP535        High Performance Multi-Port Memory Controller
XAPP536        Gigabit System Reference Design (XAPP536)
) `; e  w+ I4 ~6 X" [: q" s8 G  b  l( ZXAPP562        Configurable LocalLink CRC Reference Design&nbsp;
XAPP569        Digital Up and Down Converters for the CDMA2000 and UMTS Base Stations&nbsp;
( n  H' j- B( g9 cXAPP622        644-MHz SDR LVDS Transmitter/Receiver&nbsp;
6 G& X  r# ~8 w! Z- _4 Y- b( pXAPP623        Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors&nbsp;
XAPP634        Analog Devices TigerSHARC Link&nbsp;
% m8 m4 L4 B/ l0 EXAPP636        Optimal Pipelining of the I/O Ports of the Virtex-II Multiplier&nbsp;
XAPP689        Managing Ground Bounce in Large FPGAs&nbsp;
XAPP690        Using Block SelectRAM Memories as Serializers or Deserializers&nbsp;
XAPP693        A CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs&nbsp;
XAPP694        Reading User Data from Configuration PROMs&nbsp;
XAPP753        Interfacing Xilinx FPGAs to TI DSP Platforms Using the EMIF&nbsp;
XAPP774        Connecting Xilinx FPGAs to Texas Instruments ADS527x Series ADCs&nbsp;
( Y+ n9 M* k2 v  M# N7 EXAPP780        FPGA IFF Copy Protection Using Dallas Semiconductor/Maxim DS2432 Secure EEPROMs&nbsp;
XAPP806        Determining the Optimal DCM Phase Shift for the DDR Feedback Clock&nbsp;
XAPP909        Reference System: MCH OPB SDRAM with OPB Central DMA&nbsp;
XAPP923        Reference Design: MCH OPB EMC with OPB Central DMA&nbsp;
XAPP930        Color-Space Converter: RGB to YCrCb&nbsp;
4 L+ r9 Y1 z0 E* s/ zXAPP931        Color-Space Converter: YCrCb to RGB&nbsp;
" O5 z, Y% _3 nXAPP932        Chroma Resampler&nbsp;
9 }' s2 D7 Q1 i5 cXAPP933        Two-Dimensional Linear Filtering&nbsp;
XAPP936        Continuously Variable Fractional Rate Decimator&nbsp;
XAPP948        Hardware Acceleration of 3GPP Turbo Encoder/Decoder BER Measurement Using System Generator&nbsp;
XAPP253        Synthesizable 400 Mb/s DDR SDRAM Controller

tommywgt

能有系統的整理嗎?

造福大家靠你囉...