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AMD Geode LX 800@0.9W處理器
General Features4 a% Z% l4 ]" M. K" ?8 X+ ^: g8 G# p
■ Functional blocks include:
' y! X% S- F3 |— CPU Core
9 }, w0 k% {+ D8 ?- d$ j— GeodeLink™ Control Processor' }3 F% l$ K m6 {
— GeodeLink Interface Units
. B5 X0 m s! n& `, b— GeodeLink Memory Controller
- R, D; G/ M# S/ U l" {- v; C— Graphics Processor
1 q# E N7 D0 B: e— Display Controller
# y' o1 z& M# s5 [- m, i# X— Video Processor* f4 l" t+ d8 p2 U3 i
– TFT Controller/Video Output Port
5 {* n9 L: A& N: U p1 B— Video Input Port
$ s8 ?/ l5 w$ U9 r+ o— GeodeLink PCI Bridge d8 N6 M+ A' p( G. K5 ^8 z
— Security Block
* p9 d1 ]0 ?0 K u3 y■ 0.13 micron process
- ?3 F3 D% _* W1 O' O3 F1 G■ Packaging:1 i) [8 f* h0 k. g1 ^7 m, b% H
— 481-Terminal BGU (Ball Grid Array Cavity Up) with5 j( O' P6 Y0 h8 V* }
internal heatspreader
( ?: r* N, I" y( o+ |* c■ Single packaging option supports all features' R6 [. Y2 F0 o* ]
CPU Processor Features( a0 }5 f: l: y7 [4 Q
■ x86/x87-compatible CPU core
7 K5 i/ W: U' H9 n' X% g■ Performance:( }! @( d1 c8 ?6 H3 }
— Processor frequency: up to 500 MHz2 @( u8 S( Z7 s u# N w
— Dhrystone 2.1 MIPs: 150 to 450 i+ R' }' J7 ?2 g
— Fully pipelined FPU4 |! r! c: D' i [# C
■ Split I/D cache/TLB (Translation Look-aside Buffer):
5 Y/ e% F0 [( W2 ?8 S- j6 X— 64 KB I-cache/64 KB D-cache; I0 S S4 m8 o9 I5 }9 S
— 128 KB L2 cache configurable as I-cache, D-cache,# T2 v$ b% G, k1 u) I2 _$ W
or both
! p& C- Y- w( j( E6 |$ |5 J■ Efficient prefetch and branch prediction, d, M, B9 }* [3 m2 C7 I
■ Integrated FPU that supports the MMX® and
- Q6 `- m' {/ S5 OAMD 3DNow!™ instruction sets2 l# x1 y+ [3 {! P% Q$ ?+ e
■ Fully pipelined single precision FPU hardware with) U3 p' ^* p* _: r1 y" Z% Y
microcode support for higher precisions
, f( N ?* q% w+ V. ]4 E# G' BGeodeLink™ Control Processor
" z, ?0 d$ k5 N& a* @■ JTAG interface:& E( l0 P2 V6 b6 a$ r3 ^' N
— ATPG, Full Scan, BIST on all arrays( t! T J. {4 v9 K) N
— 1149.1 Boundary Scan compliant
% t; E, ?8 a3 M( l: H' D, v( {9 {8 s■ ICE (in-circuit emulator) interface
0 \: v5 ~$ b- o: g4 \0 w- ?$ ?■ Reset and clock control
, j+ r4 }7 I* ]9 m■ Designed for improved software debug methods and2 N" k/ }: f1 w: }% a* \6 G0 p6 _
performance analysis. d* x% q, _9 a$ ?0 w6 T8 j
■ Power Management:) \# b5 E9 z/ H
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @( x; N/ U0 _( m0 ]8 f4 g$ \) v3 r
500 MHz max power
4 r5 V/ o3 x% y9 M" F— GeodeLink active hardware power management* p# Y# n$ P: I; K6 V" {3 d+ c
— Hardware support for standard ACPI software power
% T9 b! v6 b' `- O, C8 ]management. L: C2 `5 F& M1 Y( [, a
— I/O companion SUSP/SUSPA power controls
/ l, y: B8 O& M; p8 x— Lower power I/O/ z4 O' z5 j. J) O. R, X
— Wakeup on SMI/INTR8 v/ r d; m1 I: @& [
■ Designed to work in conjunction with the
/ u* g7 G8 Z* T! U% CAMD Geode™ CS5536 companion device& u i) _. n9 y% y
GeodeLink™ Architecture" \# k0 Q) k2 h
■ High bandwidth packetized uni-directional bus for& }) x9 D: `+ L; i
internal peripherals
" T3 J) D; N2 O7 y■ Standardized protocol to allow variants of products to be5 e% h( @( f; H4 y6 V$ w' v$ i0 @# H
developed by adding or removing modules8 k' h; V j( c9 }* h" J8 d: t
■ GeodeLink Control Processor (GLCP) for diagnostics
4 y# F( q( |" N) f' _- Jand scan control9 s" `4 T# | H+ z# o+ s- m1 N
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
6 v$ l* X4 J2 @( [/ }/ j; hGeodeLink™ Memory Controller. x4 _5 `& R, j1 c
■ Integrated memory controller for low latency to CPU and
8 h# a1 \6 n) u/ |: [+ n+ fon-chip peripherals4 E# a9 Q' ^3 E3 Z6 f$ a
■ 64-bit wide DDR SDRAM bus operating frequency:- X8 C; @# o- N; _
— 200 MHz, 400 MT/S
3 t2 ?) x h& i- _; S0 H5 S7 g■ Supports unbuffered DDR DIMMS using up to 1 GB q5 [4 }; d1 J
DRAM technology
2 |/ ]! B6 D+ ^0 z■ Supports up to 2 DIMMS (16 devices max)3 x! q6 p( x; A/ I* D, E, T
2D Graphics Processor
: U5 s- N) K: M0 T■ High performance 2D graphics controller; j7 {. V/ m4 f' E+ `! x- ^
■ Alpha BLT
( X1 V; ~; h( V3 R■ Microsoft® Windows® GDI GUI acceleration:
7 m5 R7 H5 q8 e5 M7 q' K! a5 N Y) Z— Hardware support for all Microsoft RDP codes
! h! K4 R7 Z/ {■ Command buffer interface for asynchronous BLTs
3 R1 W# i. F* \' R3 s) w9 ?■ Second pattern channel support
1 f: w) v3 K) Z8 g' l& ]■ Hardware screen rotation |
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