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AMD Geode LX 800@0.9W處理器
General Features o& o4 X6 n1 f% A" N/ f
■ Functional blocks include:
( v7 `* m( W0 \2 M4 M. d, k— CPU Core
: u7 F- B8 h; f/ T— GeodeLink™ Control Processor! O9 x# \( V# y( s5 }
— GeodeLink Interface Units
! g: Q. T. j' J6 ^& H6 q( T— GeodeLink Memory Controller3 o8 z: R0 P9 v0 h4 Q3 t
— Graphics Processor0 `3 U8 P/ E1 z! g/ M$ z6 F0 V( m
— Display Controller
+ Y ^( R' i" A+ G! K— Video Processor, c! ~' M+ o, E; S9 O
– TFT Controller/Video Output Port
' ~' k8 i& `/ J1 w* X3 T4 b— Video Input Port# R9 G P7 d- h
— GeodeLink PCI Bridge5 z3 f; f+ G ~
— Security Block
5 z! ]6 N+ Z3 H( q■ 0.13 micron process
: h, D$ S N1 Z0 N4 ?4 w3 S■ Packaging:, g/ ]) ]$ p% I7 C
— 481-Terminal BGU (Ball Grid Array Cavity Up) with, N! v+ v' O$ E# C d
internal heatspreader
- j9 A+ K( @5 Y @# b1 p■ Single packaging option supports all features, u7 ], n. r- N2 ^' }
CPU Processor Features
1 G) ?- x6 j! M, j■ x86/x87-compatible CPU core
$ b: o; z( K+ I/ l■ Performance:
+ Q; V2 s3 h" K— Processor frequency: up to 500 MHz
8 ]8 g6 q: p7 b1 }— Dhrystone 2.1 MIPs: 150 to 450
1 q/ g; j! w/ p5 M5 m7 w7 V" L— Fully pipelined FPU; V9 Y/ C. m1 W1 v. Q1 {( Z' V
■ Split I/D cache/TLB (Translation Look-aside Buffer):6 X! }# x$ S t" s6 q8 M
— 64 KB I-cache/64 KB D-cache( Y: t$ d A3 ]9 f* G& E8 [6 l8 d
— 128 KB L2 cache configurable as I-cache, D-cache,; K- \ R. s* _: ~
or both2 {# W: p+ }9 |1 N* A6 u2 M0 D
■ Efficient prefetch and branch prediction: S+ x' S3 }+ |
■ Integrated FPU that supports the MMX® and: F- s9 ~: X a c' U
AMD 3DNow!™ instruction sets
/ a3 n. U0 O @3 m' y: x& ?% J* g■ Fully pipelined single precision FPU hardware with
9 y% K" C1 q& zmicrocode support for higher precisions
3 u5 ?( b$ T3 ]0 LGeodeLink™ Control Processor
/ p1 _8 T2 b) q1 H0 L I3 i■ JTAG interface:
k: j" @4 |- C— ATPG, Full Scan, BIST on all arrays
, k3 i1 |- ~' ~7 s, D# e— 1149.1 Boundary Scan compliant
! b: G3 P6 D: i, _/ l, x■ ICE (in-circuit emulator) interface6 A2 }8 D" D5 R( {# c4 M: W7 E. v8 ]
■ Reset and clock control2 Z. Y) }% [* Q1 m, C2 ]
■ Designed for improved software debug methods and8 k- z+ M5 }5 Y
performance analysis7 d+ X* F# G4 S" i0 |! u! u" {
■ Power Management:
8 z0 U6 l8 ^' T* p; G— Total Dissipated Power (TDP) 3.8W, 1.6W typical @- e, \# r6 f0 C
500 MHz max power3 L* z. N; n: D2 |1 |* b
— GeodeLink active hardware power management
0 z2 b9 p" j& {. X5 M: S+ U— Hardware support for standard ACPI software power7 _7 G* z, u/ H
management' c" U/ W" ^0 W# P9 E
— I/O companion SUSP/SUSPA power controls
3 }% p' {6 y, I. ]5 Y* j% o2 D— Lower power I/O
+ u$ i- X. ?6 S— Wakeup on SMI/INTR
; `; |) k, C# c+ x9 D■ Designed to work in conjunction with the
+ M, g- q$ s1 }1 \. K% k* IAMD Geode™ CS5536 companion device
3 z/ F3 O! j: p# M/ RGeodeLink™ Architecture
- w/ N9 [# r8 U; \/ S3 _: Z■ High bandwidth packetized uni-directional bus for8 B3 `" { r; Q7 B& E& L
internal peripherals
( z |+ D* J1 ^+ c■ Standardized protocol to allow variants of products to be9 ~* @# C( I1 q, e0 n# L9 Z
developed by adding or removing modules2 i: q2 X n# J* a
■ GeodeLink Control Processor (GLCP) for diagnostics
$ Q: {& |6 ^ K6 G2 Cand scan control
8 g u; A: N) A6 e■ Dual GeodeLink Interface Units (GLIUs) for device interconnect4 g [) n! X O# k
GeodeLink™ Memory Controller
6 B% m# M' ~( \9 n9 `■ Integrated memory controller for low latency to CPU and
, `( S7 b/ x- \5 O3 L& b' don-chip peripherals
1 _# _) P5 T4 R, d■ 64-bit wide DDR SDRAM bus operating frequency:
( ^2 g4 f; m n— 200 MHz, 400 MT/S& u% N2 R4 e4 f. D# v' x* q5 `
■ Supports unbuffered DDR DIMMS using up to 1 GB- H: M5 Q+ l8 Q, N
DRAM technology
5 E. u. G& U( z■ Supports up to 2 DIMMS (16 devices max)8 w0 u* l. c* W/ a" j7 M- C6 a
2D Graphics Processor# q' {5 e8 J+ d5 h" U' g
■ High performance 2D graphics controller# P# P& I. }. P" O( ~
■ Alpha BLT
! e5 T3 \" E- l- F5 _■ Microsoft® Windows® GDI GUI acceleration:
5 }( f& }& V. b; j( M8 D— Hardware support for all Microsoft RDP codes9 ?- Q H3 J1 w* o7 ?( U
■ Command buffer interface for asynchronous BLTs
/ s% Q8 c7 r. s■ Second pattern channel support
" z) p* H- N+ R+ R: |3 Z3 r■ Hardware screen rotation |
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