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AMD Geode LX 800@0.9W處理器 II
Display Controller- D6 v: G( q5 Q/ x% s: b7 D1 C
■ Hardware frame buffer compression improves Unified; X# m9 n' Z# X; o6 G
Memory Architecture (UMA) memory efficiency
l/ m7 n+ X# D" n( ?- z■ CRT resolutions supported:
" g$ h) O$ J) `8 D! V+ N' }6 }— Supports up to 1920x1440x32 bpp at 85 Hz
* ]9 j' P: e; D7 h3 x— Supports up to 1600x1200x32 bpp at 100 Hz' T0 G7 ~! ~4 o
■ Supports up to 1600x1200x32 bpp at 60 Hz for TFT0 }" x( e" X3 v: \; ^, E
■ Standard Definition (SD) resolution for Video Output
$ K5 m* z/ i% Y2 X7 N) vPort (VOP):
/ P3 y3 ?6 {4 ^2 E( ~/ q— 720x482 at 59.94 Hz interlaced for NTSC
- _8 G- _4 K" A$ z— 768x576 at 50 Hz interlaced for PAL
8 A# `3 V$ x7 B$ I; g6 J, \■ High Definition (HD) resolution for Video Output Port; w$ ]9 w) m" n' Q1 D3 G
(VOP):
" V* Z w( X9 p( Q, S5 S— Up to 1920x1080 at 30 Hz interlaced (1080i HD)
; u' {! W2 U$ o( g! t(74.25 MHz)
/ `0 T: C8 K) `2 A) _— Up to 1280x720 at 60 Hz progressive (720p HD)/ D" R, Q- A* B1 U
(74.25 MHz)1 C ~: u7 e# N- @, l T2 C
■ Supports down to 7.652 MHz Dot Clock (320x240
+ ~) a0 |+ d! J% {/ F# y+ E! IQVGA)
% c9 Q1 }. x Q$ S, n■ Hardware VGA
. y- W. C6 D9 q■ Hardware supported 48x64 32-bit cursor with alpha
! m* W0 k/ S% Ablending. `/ C9 O g8 C, n, r
Video Processor
7 E% O, c0 j: t* H1 k, ^5 L■ Supports video scaling, mixing and VOP, R4 [% ?# v' h9 }, k- v
■ Hardware video up/down scalar* d3 |( Q4 z0 x8 K% T5 c) f1 `
■ Graphics/video alpha blending and color key muxing: a' U' a! l: w
■ Digital VOP (SD and HD) or TFT outputs! j j q1 w4 G: [! H
■ Legacy RGB mode) z. e2 i9 t: w4 j8 p! W
■ VOP supports SD and HD 480p, 480i, 720p, and 1080i2 H) y; e0 Z1 ~
■ VESA 1.1, 2.0 and BT.601 24-bit (out only), BT.656
. A1 V* p' b! K/ Acompliant3 s$ M% D c9 p* r. H# ]& D
Integrated Analog CRT DAC, System Clock PLLs and
5 u4 K. }+ J; _ A+ DDot Clock PLL
) K/ G- w. R1 O" B5 M5 b" R# k! ^■ Integrated Dot Clock PLL with up to 350 MHz clock4 E- ]5 R/ n7 _$ o' J) o. a
■ Integrated 3x8-bit DAC with up to 350 MHz sampling' U; b/ F6 r- P8 T7 A9 n
■ Integrated x86 core PLL R& T+ }$ A; X) b- _, M! y7 P8 t
■ Memory PLL
% G+ }: k9 |- c4 g( W+ m' IGeodeLink™ PCI Bridge. M6 b" U, {' a5 H) {, |
■ PCI 2.2 compliant
4 k* x1 @, o6 ] T■ 3.3V signaling and 3.3V I/Os
) W, Z/ @6 ?3 e7 \' P7 U5 e, }■ 33 to 66 MHz operation
' S# |8 S; D; h0 O0 _■ 32-bit interface: v2 {- b, X& P( f8 K' @
■ Supports virtual PCI headers for GeodeLink devices- ]/ _" F/ T0 `. ^! I
Video Input Port (VIP)/ b% j a; o& Y9 x) N
■ VESA 1.1 and 2.0 compliant, 8 or 16-bit
. k! O! s! f F. o■ Video Blanking Interval (VBI) support
' Q. K+ s6 T! }1 F5 o% r, K/ e■ 8 or 16-bit 80 MHz SD or HD capable
) v# P* S# T0 x8 w1 }/ qSecurity Block
0 f& @1 ^: ?* T$ n/ \4 C■ Serial EEPROM interface for 2K bit unique ID and AES
) R: c8 ~) K. ~5 F(Advanced Encryption Standard) hidden key storage" E$ O* b( C. \
(EEPROM optional inside package)
, |2 C+ N; J! W/ c, a9 S5 q■ Electronic Code Book (ECB) or Cipher Block Chaining1 [" Q3 v: u0 @
(CBC)128-bit AES hardware support
5 w. W) w" R0 z, I, k) d■ True random number generator (TRNG) |
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