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AMD Geode LX 800@0.9W處理器
General Features
5 S) t+ {; H* H; y( n■ Functional blocks include:* M) s4 n6 ~3 Q; Z f' v
— CPU Core
# G G* n5 Y1 T+ B% E/ V— GeodeLink™ Control Processor7 e% P, C; [4 a/ t
— GeodeLink Interface Units
6 E) C9 ?4 a2 b: v$ T, }— GeodeLink Memory Controller( t: s' _4 X3 K( R! V/ a9 V
— Graphics Processor
; m" u- a; X1 W* b7 _) w) C E- s— Display Controller
" P$ i, E- i; P- t& I" J& F— Video Processor
: D) r1 x6 Z4 b. d# A– TFT Controller/Video Output Port
+ n* t+ v/ i+ S: j— Video Input Port1 a, ^6 |- V; P& A: f
— GeodeLink PCI Bridge
2 s! y* K% a* z( D* o! E. e— Security Block- {4 f5 x6 [& }1 o w6 {
■ 0.13 micron process
B6 v: U% r' ?% E( @5 C" e■ Packaging:
1 m* ^- j3 R8 W— 481-Terminal BGU (Ball Grid Array Cavity Up) with3 I9 ~& W$ H* R8 x c$ d3 r$ ], M1 A
internal heatspreader
2 `& V% H- y# F■ Single packaging option supports all features4 g7 g! h% k+ t0 |7 R4 i4 P
CPU Processor Features0 j1 X/ H! h7 p* Q' K( I7 a" `
■ x86/x87-compatible CPU core8 O: ]6 _3 X' G4 _# T8 B- H
■ Performance:
- `/ b/ k* T3 Z0 N$ A— Processor frequency: up to 500 MHz
+ Y0 ]5 d5 h- u8 M+ G% C8 x7 e— Dhrystone 2.1 MIPs: 150 to 450
4 `2 B, H2 w0 S! U— Fully pipelined FPU& w O* M9 K0 b: c1 P" }1 i( J. I, V
■ Split I/D cache/TLB (Translation Look-aside Buffer):7 R% P( m( D( _( q m5 ?
— 64 KB I-cache/64 KB D-cache
& y* r2 B# {( H Z— 128 KB L2 cache configurable as I-cache, D-cache,
& B2 Z$ z) {- o ?# N4 s- Mor both% W) G( J2 t/ u! e8 X3 O* l9 e; ~# K* {
■ Efficient prefetch and branch prediction
$ ?: w; v$ {7 X. i6 L2 ~■ Integrated FPU that supports the MMX® and; y& _9 U6 c* }* i5 o) \7 }; I
AMD 3DNow!™ instruction sets
a# }" _" ]" e2 f■ Fully pipelined single precision FPU hardware with. B3 ]% U6 e/ F7 ~( E: D
microcode support for higher precisions/ a4 M0 b, T% B# [
GeodeLink™ Control Processor& _, A& I0 D6 v& V: H" X- m& T7 J
■ JTAG interface:
1 W- }! m( z+ ~- q7 ]5 }8 t" `— ATPG, Full Scan, BIST on all arrays
1 b' i* E" b( _— 1149.1 Boundary Scan compliant
$ w2 V; A; U; n8 S■ ICE (in-circuit emulator) interface7 s; z/ e6 b" m/ M/ [" ~
■ Reset and clock control
- x2 l! L) |! w ?3 B( v0 |5 d■ Designed for improved software debug methods and* |5 |! b* H! k+ Z2 C9 v! l# |+ Q7 A* Q
performance analysis1 E. [, f# D; p4 C- {2 Q
■ Power Management:9 X3 _9 K% S! a4 Z, {
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @8 w# S, l0 S: u) X4 v
500 MHz max power
9 S7 H6 h+ h; W- s1 |! k— GeodeLink active hardware power management6 D8 ^$ U$ ?; }3 b9 T. G- K3 C
— Hardware support for standard ACPI software power
5 {9 e" p0 I0 v/ bmanagement
) c4 G* e" |4 S3 b— I/O companion SUSP/SUSPA power controls: v/ Q( D& g# }6 k
— Lower power I/O6 n& f" S7 |: ~$ Y
— Wakeup on SMI/INTR
" h' u& e: p3 T8 }■ Designed to work in conjunction with the
0 P) w( @# j) E- I, R; z6 q7 Q; ^- f5 Q* wAMD Geode™ CS5536 companion device' \6 O5 y4 O. k2 B; K9 a; i0 a0 _
GeodeLink™ Architecture) o% B7 R. v7 V" ]% S% F5 U4 L
■ High bandwidth packetized uni-directional bus for$ o7 u2 G9 \" x8 `
internal peripherals
+ F3 S- z5 |% V: u■ Standardized protocol to allow variants of products to be
" V9 d3 s: [4 b! U/ }8 adeveloped by adding or removing modules
d! y5 L- E# O6 i■ GeodeLink Control Processor (GLCP) for diagnostics) [9 { b+ K0 B: ?
and scan control* |+ K! q- d: ?6 ]4 ?
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
/ v# Y& ~4 t) g* S$ E( QGeodeLink™ Memory Controller
- z2 f7 R$ k' f; Y■ Integrated memory controller for low latency to CPU and3 `) C( U. @0 ^* |: g8 [2 h
on-chip peripherals: \# O3 G! {5 Y4 r) w6 g) y
■ 64-bit wide DDR SDRAM bus operating frequency:
4 t1 ]3 r2 X, w, P2 k4 v— 200 MHz, 400 MT/S
; P# m; W# G0 g9 b1 i! A■ Supports unbuffered DDR DIMMS using up to 1 GB! X$ W3 W7 x* n
DRAM technology& ]/ Q N3 x1 t- L
■ Supports up to 2 DIMMS (16 devices max)
$ l( L7 d$ U( \) @2D Graphics Processor
0 b1 o- Q4 [! k) S' b& w1 O■ High performance 2D graphics controller& L" c6 d8 ` d; O
■ Alpha BLT
6 M, o7 Z$ c6 D# z: L■ Microsoft® Windows® GDI GUI acceleration:8 M( S6 a- t' g5 Q$ {, w/ l
— Hardware support for all Microsoft RDP codes; T: k3 d" w6 K" u
■ Command buffer interface for asynchronous BLTs; ]1 _( I3 N5 j2 K
■ Second pattern channel support
/ C; g- Q7 K% w" i/ c# G/ }■ Hardware screen rotation |
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