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AMD Geode LX 800@0.9W處理器
General Features
- F- \' P$ X7 D% R. ~■ Functional blocks include:
, K1 A, }1 W9 }( \, J4 D— CPU Core5 q9 S: M- ^& c( o
— GeodeLink™ Control Processor) ^+ y u- U0 G
— GeodeLink Interface Units( X. r+ G) k6 Z$ `
— GeodeLink Memory Controller1 y+ }$ W- v3 O
— Graphics Processor! H `. e% y1 `& j
— Display Controller
0 [$ U! N6 \+ ^% g— Video Processor
# K5 \' |' V& ~9 }. M7 t& O3 k– TFT Controller/Video Output Port
) t8 a5 ~. Q# R: j4 Q— Video Input Port* P* L* c- X6 }/ R8 A; B
— GeodeLink PCI Bridge% f' z2 l( c/ |$ y8 b
— Security Block
4 \+ p2 Y+ ^& U2 p# W( P- k■ 0.13 micron process
7 f* j1 d! a T$ a■ Packaging:2 f) y% Y! R: d+ e( M5 I6 K
— 481-Terminal BGU (Ball Grid Array Cavity Up) with; [1 X: W8 H7 G& J9 b9 V
internal heatspreader
2 U. k4 X% [/ F# o, Z1 v■ Single packaging option supports all features
6 _4 w( m$ j; O; A4 H8 BCPU Processor Features2 [1 K# N" Q8 K: L
■ x86/x87-compatible CPU core ]2 S" F: @& f& R
■ Performance:& f7 Y, T; ?- |4 E
— Processor frequency: up to 500 MHz! o' _6 ^# h8 S9 A4 C
— Dhrystone 2.1 MIPs: 150 to 450- l* T% v a- U4 `5 C8 s; Y5 ]4 O
— Fully pipelined FPU
, i1 P4 r' V* \■ Split I/D cache/TLB (Translation Look-aside Buffer):
! A, E$ T# H% _2 \% L; Q— 64 KB I-cache/64 KB D-cache3 o" J; \( N9 Z: S
— 128 KB L2 cache configurable as I-cache, D-cache,
- ]: S9 d7 B% t% ^2 O3 b) xor both
5 U4 _& E+ @1 ^" L7 ]% f■ Efficient prefetch and branch prediction
7 W; L/ U* C7 H■ Integrated FPU that supports the MMX® and
4 s% Z# N; V3 [' YAMD 3DNow!™ instruction sets
5 ~4 A( D% _+ }) t; V■ Fully pipelined single precision FPU hardware with" _4 Z% v& z, b& P& [/ O" J
microcode support for higher precisions
! k) z5 z: H; `/ F) h6 i I# }0 o7 b7 ZGeodeLink™ Control Processor5 F( V) x, u# f
■ JTAG interface:6 R5 n: J7 M4 Q3 ` @
— ATPG, Full Scan, BIST on all arrays* `2 o- _# ?& S2 M+ W! J! E8 \4 T
— 1149.1 Boundary Scan compliant
9 ]& F7 _9 ^7 j @/ f■ ICE (in-circuit emulator) interface
/ Q" F, z% r# n* { D■ Reset and clock control
& P$ T- g' p& O# k. B( y) i2 b■ Designed for improved software debug methods and1 c; r3 C1 y( F, O* \% C+ s$ Y
performance analysis3 m# z/ y& J/ E# p; d/ I$ ]" P) l
■ Power Management:
' \! W; S$ n' _) p( D6 D* x& o5 `— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
$ O {9 i1 o; X1 O2 `500 MHz max power
R* d+ r- b4 a: k; \— GeodeLink active hardware power management# ^- z3 y, w, W% D9 E6 {( U
— Hardware support for standard ACPI software power, B3 F h: q. U2 Q% b
management
: ?, h+ p( R5 b' J z/ h! Z— I/O companion SUSP/SUSPA power controls: Y; R( g: A1 t3 ? t
— Lower power I/O% O9 ^1 E$ T- F* `
— Wakeup on SMI/INTR
! r4 T- t5 z( i) a F6 l" M3 c6 t■ Designed to work in conjunction with the
, A6 {* v- y7 i8 u8 U! \" a& eAMD Geode™ CS5536 companion device
% x. k! d# ^0 o0 [3 TGeodeLink™ Architecture
8 e( u) b6 x& D2 s" y' V( Q■ High bandwidth packetized uni-directional bus for# ]( O! t) a9 Z, M& r
internal peripherals$ Q( `- Z7 B0 W. {
■ Standardized protocol to allow variants of products to be
( q% {4 S6 ?- P. x udeveloped by adding or removing modules
1 Q7 G, ?& ]3 Y" t0 H$ P■ GeodeLink Control Processor (GLCP) for diagnostics" N+ ^+ _9 P+ E0 i% ]7 V
and scan control8 s% `. B4 D, I; s5 ?
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
# [7 G: Z3 l$ g3 h: C' E0 rGeodeLink™ Memory Controller! w) J$ M5 e' _9 W
■ Integrated memory controller for low latency to CPU and4 p8 S2 b2 }6 }+ p1 a
on-chip peripherals
1 {9 ^ s2 E; w: F7 S■ 64-bit wide DDR SDRAM bus operating frequency:
( N3 Q3 }* Q4 {— 200 MHz, 400 MT/S7 z% ^7 X# F; Q
■ Supports unbuffered DDR DIMMS using up to 1 GB
5 |$ F: g) H/ Y2 d' |DRAM technology
5 w ?' @ @7 G- u" @8 E3 _■ Supports up to 2 DIMMS (16 devices max)
- L; C: K4 o* o" J. P7 I5 F: S2D Graphics Processor$ t6 B- [3 m% B: r3 T$ ^
■ High performance 2D graphics controller, _! t, e; [& t! b- z9 S
■ Alpha BLT
% K* z( A3 O" [5 V1 p■ Microsoft® Windows® GDI GUI acceleration:, z: f2 {9 l& X C7 a
— Hardware support for all Microsoft RDP codes: ?3 \8 u& e& `; k. U0 J2 t
■ Command buffer interface for asynchronous BLTs
* C. f$ {5 H; T' R# A■ Second pattern channel support
, F# l, h$ P% i# p* ^3 V0 I■ Hardware screen rotation |
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