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AMD Geode LX 800@0.9W處理器
General Features
' m" r5 l- \; {! }■ Functional blocks include:
/ m3 W' k% w1 `— CPU Core& X4 S- |- x' ~: R+ h6 h% t$ G
— GeodeLink™ Control Processor
+ Z% ?$ E: z! [% |— GeodeLink Interface Units
( a8 g3 v3 P2 a; V6 A7 _— GeodeLink Memory Controller
8 h8 i4 h( m+ I: E— Graphics Processor3 y+ D7 w' d# {1 ?
— Display Controller8 q7 y( d6 h( ?3 z ^
— Video Processor
' P; V3 @+ p! j4 ?7 A5 h– TFT Controller/Video Output Port
% {: \, n/ l% v— Video Input Port. B' c2 ~ X, t) j* N0 @
— GeodeLink PCI Bridge, n; x9 y5 V* n( U* a+ e
— Security Block+ |% m- X5 O! ~1 R
■ 0.13 micron process
1 S& F9 j: j, o9 W4 v■ Packaging:
. O1 O3 R$ a" Y% d: s' k— 481-Terminal BGU (Ball Grid Array Cavity Up) with
" M7 }! E; c: F6 yinternal heatspreader5 x f B) t }0 t t
■ Single packaging option supports all features
7 K5 T! y4 Q4 {CPU Processor Features8 l7 j9 K5 R3 ]5 w
■ x86/x87-compatible CPU core' H7 [2 O& b- [5 O" X
■ Performance:
6 I0 z+ o4 z- }# k— Processor frequency: up to 500 MHz
2 t K$ p; j: Z) s— Dhrystone 2.1 MIPs: 150 to 450
, t& d7 ~' J, R' D0 R0 N— Fully pipelined FPU
4 x# ~# K; r$ ~3 y7 _■ Split I/D cache/TLB (Translation Look-aside Buffer):
6 v# N# k7 n0 o, W% c1 K3 @' r" F R— 64 KB I-cache/64 KB D-cache
& w% r+ m4 G5 O' V+ Q2 @+ g— 128 KB L2 cache configurable as I-cache, D-cache,
2 K0 j: K8 s* a7 nor both
' Z/ M# Q! d% X: Z■ Efficient prefetch and branch prediction
" x/ w$ D: b) s2 @5 [6 v) O■ Integrated FPU that supports the MMX® and
, O. t. @ w2 Q8 Y% Q- zAMD 3DNow!™ instruction sets* t, _0 K) ^7 ~) z7 s
■ Fully pipelined single precision FPU hardware with
9 z# }" G3 |2 nmicrocode support for higher precisions0 Q/ p3 r. }1 f
GeodeLink™ Control Processor
& H- n) T; x3 \8 Y■ JTAG interface:
: w, K+ A f+ o& G, v8 L— ATPG, Full Scan, BIST on all arrays
; `3 [; g# w7 a! w6 i ?: X— 1149.1 Boundary Scan compliant% ^: h# Z( o3 l
■ ICE (in-circuit emulator) interface
, m( U' `% f9 q7 L- p/ M# v/ J8 }2 @■ Reset and clock control
; v4 ?8 @% P6 x1 x■ Designed for improved software debug methods and" A; E8 B+ U; p1 h. w* u/ J
performance analysis
8 i/ U9 ]* [( o, c* E& P■ Power Management:
e+ a0 r% R* ?& F2 }— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
3 l; a* J7 f0 Q' }: x$ W$ e500 MHz max power+ f" t9 Q5 c0 o/ [2 H) F
— GeodeLink active hardware power management
; N/ f; ~6 e4 ?( I# j5 Q) }— Hardware support for standard ACPI software power
$ @9 N2 M8 m7 G. ?' k9 Gmanagement# g8 Q, I2 {4 W8 G+ p: ~# w8 [
— I/O companion SUSP/SUSPA power controls
6 } u5 |5 y# R— Lower power I/O
) B( g5 J' O: b1 H8 r; L, _7 U— Wakeup on SMI/INTR
8 F6 N+ v- s% `0 s$ Y■ Designed to work in conjunction with the
' J: U3 u m; o& VAMD Geode™ CS5536 companion device
! f7 h! x& |( S, _5 w$ D& h" y% n/ cGeodeLink™ Architecture
: ^8 V. N9 h. F) j1 }: M■ High bandwidth packetized uni-directional bus for0 w6 z! ~6 S' Z1 W: W& t
internal peripherals
& N) o& ^. }" i+ }7 V7 a■ Standardized protocol to allow variants of products to be
$ Q. O0 F' B6 u5 zdeveloped by adding or removing modules
! A" a" M3 G6 p; w& l' Q5 g1 p■ GeodeLink Control Processor (GLCP) for diagnostics
8 ~) U3 J* V) k: Y( j8 D% jand scan control
6 K$ h9 ~1 W4 p& Y4 M! Z■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
# [1 b0 Z2 q% \" ]" |6 J( T0 i. }GeodeLink™ Memory Controller
9 i+ \8 Y! m- F0 G■ Integrated memory controller for low latency to CPU and. ^' S& |8 Z. a: I1 I& K
on-chip peripherals. @' R# j9 n% C, ~+ r2 I% A2 U
■ 64-bit wide DDR SDRAM bus operating frequency:
% y W7 X! L4 E0 [* h. ^% s0 Y— 200 MHz, 400 MT/S
; V4 g3 K" l) U+ n3 V3 d■ Supports unbuffered DDR DIMMS using up to 1 GB2 }3 n/ I9 ]) T; }
DRAM technology
9 S" i L/ M6 S: F2 G■ Supports up to 2 DIMMS (16 devices max)
( r/ z, p! I; B; V& p8 B0 @2D Graphics Processor
3 X4 A' R2 l4 ]5 Y9 F' p■ High performance 2D graphics controller* m7 k5 {$ K- G) g
■ Alpha BLT5 [5 Z( q+ j" x' ^! l
■ Microsoft® Windows® GDI GUI acceleration:) h& x5 i$ z. s. r, I, T
— Hardware support for all Microsoft RDP codes
, v& {1 O7 H% O( `■ Command buffer interface for asynchronous BLTs
4 [: o1 A* G" X4 Y3 [6 n1 y. A■ Second pattern channel support
9 C# W9 L. j; }; H0 A; t2 h/ H; q1 z% u■ Hardware screen rotation |
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