verilog 觸發問題

peliuya

今我欲使 sys_signal 此輸入訊號在正緣時，使 rst_B1 訊號為 High。
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正緣過後（即下一個 system clk(50 MHz)），rst_B1 復歸為 Low。
+ N" h/ X2 J+ W, E
sys_signal 此訊號為  60 Hz , Duty ratio 為 50 ％ 的方波
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請問應該如何撰寫此段程式？

nesty.tseng

always @(posedge CLK_50M or negedge PORB)
- y4 c0 F6 j/ |8 ybegin
  if(!PORB)
    sys_signal_d1 <= #1 1b'0;
  else
5 i) ^* c* Q6 [    sys_signal_d1 <= #1 sys_signal;
9 J- e: v" _  ~4 ?+ ~end

assign sys_signal_pul = sys_signal & ! sys_signal_d1;
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always @(posedge sys_signal or negedge sys_signal_pul)
! x) O1 I0 [% s  V$ ^" o: rbegin
  if(!sys_signal_pul)
8 C7 ]2 ^% `+ k8 W: `. F' [    rst_B1 <= #1 1'b0;
3 p- C# W' O4 Y# n2 p  else
  }! B. u0 r; Z# T( b% H    rst_B1 <= #1 1'b1;
end