Optimization on ESD Clamp Circuits in a 0.13-μm Technology

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Optimization on NMOS-Based Power-Rail ESD Clamp
1 I$ M" V" e0 o4 ^3 cCircuits with Gate-Driven Mechanism in a 0.13-μm
CMOS Technology

# }* Z3 q7 f8 t& DAbstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
5 f! M) z% j6 @" A- z: Vdesired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.

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IV. CONCLUSION
The designs with 3-stage-inverter and 1-stage-inverter
controlling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
( F$ p- B* @8 e$ ]) E+ i! n5 Fhaving snapback and no snapback operations, also were codesigned
with different controlling circuits to realize the
" D9 c- O: J. i: Rimpact on their required performance. According to the
# ~, Q! D, ?4 fexperiments and analyses, the 3-stage inverters can slightly
! K- c  a, D5 N4 Z/ yincrease the ESD robustness, but they also can dramatically
) m. m1 t  w5 T, j) l9 h& J$ n' u3 O/ Psacrifice the mis-trigger and latch-on immunity. The 1-stage
inverter should be an appropriate and reliable candidate for the
power-rail ESD clamp circuits.