Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
- l- m' X  Q6 ]- V( OCircuits with Gate-Driven Mechanism in a 0.13-μm
- B8 S6 L1 v2 |) ACMOS Technology
0 q' a" u; h6 c2 ?
Abstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
+ \; q" k& h& S/ S3 Adesired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.

) p+ c0 x) x, m$ z. ?7 ]* i注意：内容有一定深度，初学者可能看起来有些困难。

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semico_ljj

IV. CONCLUSION
The designs with 3-stage-inverter and 1-stage-inverter
controlling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
' H+ a" A/ a4 o6 e6 @4 `having snapback and no snapback operations, also were codesigned
4 h  K3 R9 ?( k7 Cwith different controlling circuits to realize the
impact on their required performance. According to the
* y/ D2 w% P" Mexperiments and analyses, the 3-stage inverters can slightly
) j0 T' n( [" h/ yincrease the ESD robustness, but they also can dramatically
0 ~- E# L% }" lsacrifice the mis-trigger and latch-on immunity. The 1-stage
7 H$ a" w0 M# W5 W7 Winverter should be an appropriate and reliable candidate for the
6 K8 [1 ~! p1 P8 cpower-rail ESD clamp circuits.

aicder

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kevin5461

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layes2

還要回復啊。希望能學到一些東西，謝謝！

jstsai

very useful, Thanks for your sharing...........

chkd002

正在學這方面的知識，多謝分享好東西！