Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
+ J9 {5 |+ ~: o/ oCircuits with Gate-Driven Mechanism in a 0.13-μm
CMOS Technology
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# t) a; b; S5 l) w* P" z6 i  x8 J: u) cAbstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
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1 d  G* Z/ ?3 j0 j: G4 c( ?6 ?注意：内容有一定深度，初学者可能看起来有些困难。

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semico_ljj

IV. CONCLUSION
The designs with 3-stage-inverter and 1-stage-inverter
controlling circuits have been studied to verify the optimal
1 a  f* V) N1 a1 ~design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
having snapback and no snapback operations, also were codesigned
with different controlling circuits to realize the
( [5 z' A% ^+ E% ?9 Fimpact on their required performance. According to the
experiments and analyses, the 3-stage inverters can slightly
increase the ESD robustness, but they also can dramatically
. _2 t+ `2 \5 Gsacrifice the mis-trigger and latch-on immunity. The 1-stage
inverter should be an appropriate and reliable candidate for the
2 `; z7 n3 h# H( e/ u: i( Ypower-rail ESD clamp circuits.

aicder

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kevin5461

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layes2

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jstsai

very useful, Thanks for your sharing...........

chkd002

正在學這方面的知識，多謝分享好東西！