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發表於 2008-11-26 21:59:05
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IV. CONCLUSION! X E4 g; C1 n, x# R
The designs with 3-stage-inverter and 1-stage-inverter
3 \% j1 i$ s m$ @ K. u% \, wcontrolling circuits have been studied to verify the optimal: Q7 ~ x% k& ?# `8 J; M8 ~* ]
design schemes in NMOS-based power-rail ESD clamp
6 p! x3 f/ R2 h& Pcircuits. In addition, two ESD clamp NMOS transistors,% P& L# C- v# m
having snapback and no snapback operations, also were codesigned' \( p) i! A4 r9 G5 ], ~
with different controlling circuits to realize the2 H; X/ [. ~( D. Y% q+ y
impact on their required performance. According to the
5 m+ U. D L9 [' s3 y7 A. E# [experiments and analyses, the 3-stage inverters can slightly
& B( b9 b$ {5 x$ Z% }increase the ESD robustness, but they also can dramatically+ P/ I: T1 p! O3 Q
sacrifice the mis-trigger and latch-on immunity. The 1-stage
! J" i) A" `7 n+ w3 Einverter should be an appropriate and reliable candidate for the
6 @7 c% k _8 t w& h W8 G4 tpower-rail ESD clamp circuits. |
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