Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
Circuits with Gate-Driven Mechanism in a 0.13-μm
CMOS Technology

; k! M$ ^4 j( S& V  n6 q) k" m9 oAbstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
, U3 g, p1 Q* d4 I; L3 b# C# o# q$ ^/ zdesired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
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$ T1 S0 d+ x+ M& ]3 |注意：内容有一定深度，初学者可能看起来有些困难。
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semico_ljj

IV. CONCLUSION
# n- k% s" e( B0 p" bThe designs with 3-stage-inverter and 1-stage-inverter
controlling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
having snapback and no snapback operations, also were codesigned
3 g' j$ i1 [7 W0 p% i3 h) ]8 z5 b! Vwith different controlling circuits to realize the
. \- l, |* j( E  v* y7 V* ^3 D2 oimpact on their required performance. According to the
' k7 o7 ^( e5 p( A  s* [experiments and analyses, the 3-stage inverters can slightly
increase the ESD robustness, but they also can dramatically
, h/ l9 I5 M9 I5 R5 Y0 m8 J3 Dsacrifice the mis-trigger and latch-on immunity. The 1-stage
+ v8 i) ^. e7 H- J1 uinverter should be an appropriate and reliable candidate for the
0 n. k/ R2 `" n$ k' @4 }) J2 bpower-rail ESD clamp circuits.

aicder

very good!
# P  V* p( \+ `+ uDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD

kevin5461

好東西~~謝謝這位大大的分享~~~~~~~~~~~~~

layes2

還要回復啊。希望能學到一些東西，謝謝！

jstsai

very useful, Thanks for your sharing...........

chkd002

正在學這方面的知識，多謝分享好東西！