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發表於 2008-11-26 21:59:05
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IV. CONCLUSION
& g: e( Z5 s$ p7 GThe designs with 3-stage-inverter and 1-stage-inverter. e: w2 Z6 t) a# G4 P9 }, f% ~0 a5 c
controlling circuits have been studied to verify the optimal8 g9 M0 R8 e+ r- m3 d+ a
design schemes in NMOS-based power-rail ESD clamp, G4 X8 e0 {4 z3 [
circuits. In addition, two ESD clamp NMOS transistors,! B* S4 p1 P' P8 Z v
having snapback and no snapback operations, also were codesigned: E* Z9 {1 o( V0 r& M
with different controlling circuits to realize the$ J: g" }& o0 r9 c% J0 i1 Q: q/ x$ I. V
impact on their required performance. According to the! O$ u5 U7 D4 c7 J
experiments and analyses, the 3-stage inverters can slightly0 c$ `3 i) p. Q7 _
increase the ESD robustness, but they also can dramatically: p" P7 m/ D0 |1 ]6 }3 g* H
sacrifice the mis-trigger and latch-on immunity. The 1-stage
- K$ W9 Q( e% c% S7 n. Pinverter should be an appropriate and reliable candidate for the3 r* S" o' f* s1 f* B0 F' B9 b4 n
power-rail ESD clamp circuits. |
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