Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
Circuits with Gate-Driven Mechanism in a 0.13-μm
CMOS Technology

4 i- I4 ^* N; E; P( U' i4 iAbstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
& H' L( N. E/ u3 D+ _5 M# A# j7 G* Fdesired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
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chkd002

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jstsai

very useful, Thanks for your sharing...........

layes2

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kevin5461

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aicder

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semico_ljj

IV. CONCLUSION
6 t7 N) f! D! ^& T5 h/ @1 m7 \The designs with 3-stage-inverter and 1-stage-inverter
; I" K: J' |% s! E8 Dcontrolling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
8 z( V! x. \; r% b+ Scircuits. In addition, two ESD clamp NMOS transistors,
having snapback and no snapback operations, also were codesigned
with different controlling circuits to realize the
+ R3 d# Q! ]6 d, O# \/ Mimpact on their required performance. According to the
% E7 ?7 X$ T) l: t4 Q2 L4 Eexperiments and analyses, the 3-stage inverters can slightly
increase the ESD robustness, but they also can dramatically
sacrifice the mis-trigger and latch-on immunity. The 1-stage
inverter should be an appropriate and reliable candidate for the
power-rail ESD clamp circuits.