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發表於 2008-11-20 11:53:00
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On-Chip ESD Protection for Integrated Circuits
1 S8 O& n1 N1 K1 l" ]1 Z, AAn IC Design Perspective
; T! Z! C- d0 g. @- A9 i2 ]! E! I4 j; d# Z5 m# T9 }
by4 _ O6 k3 C* v% Y) w- {
Albert Z.H. Wang
! K- E* [0 J: aIllinois Institute of Technology, Chicago, USA7 F2 o1 `" j! l: b( ~
0 w" w* s, i/ ^9 L4 |Dedication.
u9 h v) V1 yAcknowledgements.
) B; K/ S s) ]- e; t% lPreface.
4 b5 V6 T- Y$ o* u$ A0 o" u3 ?1. Introduction. 2. ESD Test Models. 3. ESD Pr
1 p3 F) N& d; g% E# ADevice Solutions. 4. ESD Protection Circuit Solutions. 5. Advanced ESD Protection; Mixe% n# s; R: E6 x# x6 ~
and Whole-Chip ESD Protection. 6. ESD Failure Analysis and Modeling. 7. Layout and Te
8 @! c2 e% q f0 {3 J- LInfluences on ESD Protection Circuit Design. 8. ESD Simulation-Design Methodologies. 9( P+ |' G* t/ {" g0 Z
Circuit Interactions. 10. Conclusion Remarks and Future Work.
. k: e8 B m* f- R8 G: @+ _) bAppendix A: Summary fo
$ J/ j2 s' z3 ?4 a! d# DStandards. References. 8 ]! b3 Z* D& `; ?3 u
Appendix B: Commercial ESD Testing Systems.
* n& t; i: s, I; u7 o% }Appendix C: E
; T6 a' |7 u5 ]$ ^: h5 zProtection Circuit Design Checklist. Index. |
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