Stanford_Mark Horowitz_Digital MOS Integrated Circuits

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Lecture 1 - Intro and Modeling   
Lecture 2 - RC Modeling and Calibration        
4 X; `$ S+ h8 F# TLecture 3 Memory Design   
' E( l# \, C; ]. p- I4 T( l1 zLecture 4 - Delay Optimization and Logical Effort   
Lecture 5 - Decoder Optimization   
; l( \. C3 ?2 E. ], vLecture 6 LE in the Real World   
6 Y# x9 G( i  M. Y: B& q/ X) `Lecture 7 Lower LE Gates   
- ?' L4 g1 T  h: \1 E0 A1 aLecture 8 - Low Field MOS Transistor Model   
/ L, d3 E( `) E/ QLecture 9 - High Field MOS Transistor Model  
Lect 10 - Using MOS Models   
Lect 11 - Cap Models   
Lect 12 SRAM Column Circuits   
' |, L* g; t, O/ t0 Z8 k8 ALect 13 What Makes Gates Digital
* }: ^8 V7 L) t* SLect 14 Diff Pairs - Current Steering Logic
Lect 15 - Static Sense Amplifiers   
Lect 16 MOS Matching Clk SenseAmps   
Lect 17 SRAM Noise Margins / Noise   
Lect 18 - Timing Gen and Array Partitioning   
Lect 19 Adv Clocked Logic   
Lect 20 Low Swing SRAM   
Lect 21 - Introduction to Solid State   
Lect 22 Threshold Voltage, Leakage and Tunneling

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