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CMOS Transistor Layout
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7 y' d ]( _* q1 zCopyright © 2005- _% l2 A9 E+ j+ x* _
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Table of Contents6 F& j4 G; ~8 z- |: D+ b& S
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Preface% e8 B0 w' Z, U) k' d; I" K, z
1. Introduction .................................................................. 1( A+ I* m, T0 v# O6 M
2. MOS Transistors ........................................................... 2. M2 N8 x- z3 _- t
3. Fabrication of MOS Transistor ..................................... 5, X' i# I8 P7 O6 m
4. Layout a Single Transistor .......................................... 113 b/ [7 [; b3 q7 |3 C$ l$ G& V
First Stroke The basic transistor layout ..................... 127 g2 ^5 i3 `# P: Q# p+ b) o
Second Stroke Compact the transistor layout ................ 137 ^7 F+ V. O- x8 X
Third Stroke Speed up the transistor ........................... 17" J# k Q; g8 q8 T
Fourth Stroke Clean up the substrate Disturbances ...... 20* V0 c7 W# ?" _7 [$ A/ z
Fifth Stroke Balancing area, speed and noise ............ 26+ Q# k/ e5 |, h+ i3 l) g& M" `
Sixth Stroke Relief the stress ...................................... 29' W- z* F3 X; y8 ~, _
Seventh Stroke Protect the gate ...................................... 30
5 u# G2 w `/ `" `Eighth Stroke Improve yield ..........................................32! g \! V; x" [, t6 |
5. Layout Several Transistors ......................................... 34$ T+ x. `. L {) N% S
Eighth Stroke Improve yield...........................................35
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Ninth Stroke Close proximity .......................................36" \8 e# X9 u: e3 l+ N; Z
Tenth Stroke Interdigitated layout ............................... 36% F* @3 S; @4 x" U, B
Eleventh Stroke Dummy transistor ................................... 416 T5 c3 a& @6 o5 W& Q
Twelfth Stroke Two-dimension interdigitated layout ..... 43% Q- U9 ^- ?7 w, O
Thirteenth Stroke Guard ring for the matched transistors ... 45
0 x2 G/ Y u1 B* u( g! gFourteenth Stroke Keep NMOS away from N-well ............ 45" M; ]2 z9 n: R. [0 I/ H! W
Fifteenth Stroke Orientate the transistor ........................... 46
. P$ E# G, T0 P- M' X6 c$ s: O% YSixteenth Stroke Match the interconnects ......................... 47
' a) k) j$ F" T* ]1 L& l+ sSeventeenth Stroke The unmatchable .................................... 50
7 t& k1 C4 ` J2 a# h( d6. Verifying the Transistor Layout ................................. 529 @% _) ~7 x$ Z0 o2 M1 ~5 ?
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[ 本帖最後由 semico_ljj 於 2008-11-1 04:01 PM 編輯 ] |
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