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CMOS Transistor Layout- {3 ?7 z; h' a7 |8 J- s
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Copyright © 2005
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Table of Contents3 `2 G' K+ U; l
) U; o3 a1 v- A* [% ?8 D- E# LPreface
+ K* ^0 w# w' W& ]4 u" {2 g7 ~8 G0 b1. Introduction .................................................................. 1
& q2 {* m' p* O1 _2 E% {9 Y4 ~0 j2. MOS Transistors ........................................................... 2
6 U R5 @8 J! x0 i3. Fabrication of MOS Transistor ..................................... 5
: d9 O) r0 P1 C4. Layout a Single Transistor .......................................... 113 D2 J6 ?1 G! o/ f' u1 c% b. Q
First Stroke The basic transistor layout ..................... 12
3 i9 X& e9 |3 S+ N9 mSecond Stroke Compact the transistor layout ................ 13( p8 p) B8 T2 X! a/ x& u
Third Stroke Speed up the transistor ........................... 170 k6 O* b8 s% Y/ c0 s
Fourth Stroke Clean up the substrate Disturbances ...... 20
* e' P3 T* |% H! F3 `3 V. ZFifth Stroke Balancing area, speed and noise ............ 265 ?4 ?5 {' u1 ]
Sixth Stroke Relief the stress ...................................... 29
; w8 B- `9 v* b8 MSeventh Stroke Protect the gate ...................................... 30" h3 ~' w) j9 {8 ^5 V: U; S4 M
Eighth Stroke Improve yield ..........................................32
1 v& K/ Q1 X% v1 d" z$ n+ E5. Layout Several Transistors ......................................... 34
3 @9 [0 u8 I! Z1 \6 e0 H* C+ N7 MEighth Stroke Improve yield...........................................352 M1 n( n; {& z. R
Re-visit, _3 ^% I% M0 ?. n, M
Ninth Stroke Close proximity .......................................362 p) Z' ^1 P1 \; k( y) D
Tenth Stroke Interdigitated layout ............................... 36
% _9 Q" E8 I6 E9 E& vEleventh Stroke Dummy transistor ................................... 41) {" X8 }1 |4 L
Twelfth Stroke Two-dimension interdigitated layout ..... 43
$ M+ x7 u/ P( r0 o& `( V( ZThirteenth Stroke Guard ring for the matched transistors ... 45
D$ s$ y; G- A( B' ~4 lFourteenth Stroke Keep NMOS away from N-well ............ 45+ ?0 F$ t" R) X# n) ]
Fifteenth Stroke Orientate the transistor ........................... 46
: n" @' [* z+ n( I6 E- mSixteenth Stroke Match the interconnects ......................... 47' m' [" F7 C/ f' r- l+ s {
Seventeenth Stroke The unmatchable .................................... 50
8 W( D9 x$ y) ]% E; S+ {! l6 N6. Verifying the Transistor Layout ................................. 52
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[ 本帖最後由 semico_ljj 於 2008-11-1 04:01 PM 編輯 ] |
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