Chip123 科技應用創新平台

 找回密碼
 申請會員

QQ登錄

只需一步,快速開始

Login

用FB帳號登入

搜索
1 2 3 4
查看: 2998|回復: 4
打印 上一主題 下一主題

[問題求助] 论文翻译

[複製鏈接]
跳轉到指定樓層
1#
發表於 2008-4-21 13:36:31 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
soc的博士论文翻译,很多专业词汇偶没有头绪,求帮助:
: G& f' v8 d, |$ ~% c" U. h( [( l5 p% t/ J
Multi-Layer Interconnect Performance Corners for Variation-Aware Timing Analysis
分享到:  QQ好友和群QQ好友和群 QQ空間QQ空間 騰訊微博騰訊微博 騰訊朋友騰訊朋友
收藏收藏 分享分享 頂 踩 分享分享
2#
發表於 2008-4-21 16:25:34 | 只看該作者
Can it find in IEEE ? 7 `+ O$ _* m! r  E: s! w9 j
Please give me the full name of  博士论文 , let's try to solve it  D2 X( l- U3 c/ d: w0 K
5 J. `8 d- N2 h  P
[ 本帖最後由 masonchung 於 2008-4-21 04:29 PM 編輯 ]
3#
發表於 2008-4-21 23:56:35 | 只看該作者
這應該是APR的論文
4 a1 @6 f0 ]4 T( {" Y$ P
. f+ \# N, S, P2 D4 D" i6 c  j8 b% o- L  T
Abstract:( p+ v. g/ q0 F
Parasitic interconnect corner methods are known to                    
$ t; L5 W" m# M5 H1 Sbe inaccurate. This paper explains the sources of their errors and! P' l2 I. r7 ?: C1 t* d) D% G
shows that errors in excess of 22% can occur in the predicted1 c2 @8 r0 W% {
corner delays of a multi-layer stage in the presence of process
" F' F2 f. [" {variations. It is shown that exhaustive corner search methods are
2 O7 @0 h, J' y/ m  N* F3 G; Winfeasible in practice as they have an exponential complexity in! }8 u. Y! B1 t2 B
terms of required SPICE simulations with respect to the number
4 \6 }0 @, |7 C5 zof layers a stage is routed through. This exponential complexity4 I% \: ~4 p4 h
is reduced to a linear one with a new simulation-based search6 n# W' D; O) z" e3 L5 q- f
method with the aid of stage delay properties. The ideas behind! ?% W& p* ^; @2 L5 O
the simulation-based methodology are shown to be expandable- [( Y# G2 c. z" L+ Z+ ~/ L2 p
to an analytical-based multi-layer performance corner location7 I1 _0 w( U5 A/ K7 s
methodology. The simulated best/worst case delays based on these
% c# H( x. U; j2 Ranalytical corners produce errors below 4% as compared to the
( H$ b' d0 S: ]/ ?& h( P5 v! Y; k6 C! Zexhaustive search simulation based method.
, ^4 M" @+ U) K+ C$ l! O; k. ^7 c. m8 y( W! J1 @
[ 本帖最後由 masonchung 於 2008-4-22 12:01 AM 編輯 ]

本帖子中包含更多資源

您需要 登錄 才可以下載或查看,沒有帳號?申請會員

x
4#
 樓主| 發表於 2008-4-22 12:28:19 | 只看該作者

偶是门外汉

对的哦,就是这篇
- U9 L9 A3 C2 u) d7 g8 A3 O4 k很多专业词汇我不懂怎么翻啊4 t, {4 c1 x) T: F8 N
( y; q# [( x& H/ V7 ?" W
the name of this paper:    Multi-Layer Interconnect Performance Corners for Variation-Aware Timing Analysis, J; t* g+ v+ a9 f
5 D0 E9 @6 S& Y6 L% f$ r
比如说:2 ]" B2 g7 s' Z7 w  o, E" U2 Z2 A
Performance Corners- n2 \5 e/ S6 ?7 e( C
Variation-Aware, t! j. p9 G1 @
stage
& j9 k& @+ M: w5 @/ ?+ vcorner
1 O) Q3 l$ m5 a8 Q之类的
; R# X% F! [+ N: J7 j) J' w1 s" l& f8 m$ e7 T0 H0 E) K9 A: L
tx们帮帮忙啊
5#
發表於 2008-4-25 21:20:49 | 只看該作者
建議你可以到EDA設計或RD討論區發問 8 y, C2 j& S0 p" y# d
或許可以得到較多回應哦  ^^
您需要登錄後才可以回帖 登錄 | 申請會員

本版積分規則

首頁|手機版|Chip123 科技應用創新平台 |新契機國際商機整合股份有限公司

GMT+8, 2024-5-15 12:33 AM , Processed in 0.112014 second(s), 19 queries .

Powered by Discuz! X3.2

© 2001-2013 Comsenz Inc.

快速回復 返回頂部 返回列表