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這應該是APR的論文
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7 N2 O% G( H8 X. Y( @; jAbstract:
8 q$ ~9 }' M+ p c+ \1 l3 {Parasitic interconnect corner methods are known to 5 v4 }1 Q) @' t# N& d: ~* ~" x3 t
be inaccurate. This paper explains the sources of their errors and6 `6 y1 I) s! m3 \" ^% p( ^
shows that errors in excess of 22% can occur in the predicted
1 {4 i0 i/ w0 I" X8 W0 Y7 q# wcorner delays of a multi-layer stage in the presence of process$ W! m' i# j1 k/ t: h/ A
variations. It is shown that exhaustive corner search methods are
: H3 b0 C! T* ?- q9 x5 H+ ~3 Einfeasible in practice as they have an exponential complexity in* w3 E* \2 x/ {3 y* a; j
terms of required SPICE simulations with respect to the number
' ]( z: D# \+ g( D9 mof layers a stage is routed through. This exponential complexity4 {9 d( t8 d9 s2 }
is reduced to a linear one with a new simulation-based search
0 P _2 v5 u o$ J; F% Z# qmethod with the aid of stage delay properties. The ideas behind$ S9 S6 u# S t) Y
the simulation-based methodology are shown to be expandable
B4 n1 Z+ g2 U, mto an analytical-based multi-layer performance corner location/ K6 Y, N0 x* I9 m
methodology. The simulated best/worst case delays based on these l% d" [8 E5 v1 g
analytical corners produce errors below 4% as compared to the
Q4 D& @1 ]7 d" t+ \6 Gexhaustive search simulation based method.
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7 I, ~$ x1 h" h* l2 u& Q) L; m[ 本帖最後由 masonchung 於 2008-4-22 12:01 AM 編輯 ] |
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