(ESD) Failure Mode, Relibility and case study.

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8 Failure Modes, Reliability Issues, and Case Studies 228
, n( y* P7 E' r! ]" d7 C! V% \6 N8.1 Introduction 228
8.2 Failure Mode Analysis 229
8.3 Reliability and Performance Considerations 238
8.4 Advanced CMOS Input Protection 239
8.5 Optimizing the Input Protection Scheme 242
8.6 Designs for Special Applications 249
  A) ~. M: J2 @" r) C8.7 Process Effects on Input Protection Design 253
8.8 Total IC Chip Protection 255
8.9 Power Bus Protection 256
8.10 Internal Chip ESD Damage 258
8.11 Stress Dependent ESD Behavior 263
  y0 A6 |# K6 O. B2 f: W) c8.12 Failure Mode Case Studies 267
8.13 Summary 271
) Y) z+ ~8 k) o& `& j: g3 aBibliography 272
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