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8 Failure Modes, Reliability Issues, and Case Studies 228% I, R' E; e1 h8 P
8.1 Introduction 228) E* o E) k1 l9 G; F& _
8.2 Failure Mode Analysis 2292 d: q$ J; \' z, G8 R
8.3 Reliability and Performance Considerations 2389 D6 o" _( a' x, X4 T- ]0 u
8.4 Advanced CMOS Input Protection 2393 z6 O( O+ `) N& o, D7 F. e3 E$ x6 A
8.5 Optimizing the Input Protection Scheme 242
( _6 a- D) j2 G8.6 Designs for Special Applications 249
$ h8 D2 u& x$ U9 p b0 @' u" L+ S4 i8.7 Process Effects on Input Protection Design 253' P& @8 @* d5 h$ i
8.8 Total IC Chip Protection 2550 _8 Q1 S- Y+ I
8.9 Power Bus Protection 256
& \/ u9 l4 y4 m- ]. A) n8.10 Internal Chip ESD Damage 258. x6 h0 n5 O- k9 P* e7 w
8.11 Stress Dependent ESD Behavior 263
+ W4 _8 g. ~% \ w( f2 ~4 a8.12 Failure Mode Case Studies 2672 I$ c2 O6 E: W& t
8.13 Summary 271! K8 L/ L2 j7 C: T4 o. C7 y5 t2 `
Bibliography 272. c& J5 L( Z5 Z/ a8 |5 F
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