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8 Failure Modes, Reliability Issues, and Case Studies 228* }; x$ D1 h$ H. s1 b4 o; N; Q6 ]
8.1 Introduction 2288 e j0 w% k/ |4 t$ U
8.2 Failure Mode Analysis 2298 v, ?% h$ ?% @# J/ P; S6 P
8.3 Reliability and Performance Considerations 2386 R" g; b5 f$ j0 G2 ]( b/ {
8.4 Advanced CMOS Input Protection 239
, W* _3 v" j+ O. z/ {8.5 Optimizing the Input Protection Scheme 242
, o \3 e$ [( [% z8.6 Designs for Special Applications 249
0 `; X- g! S- |8.7 Process Effects on Input Protection Design 253+ W+ n! p; \6 g5 b
8.8 Total IC Chip Protection 2557 c+ r0 O6 n& l! W4 {: E: Z) F! u: \
8.9 Power Bus Protection 256
2 q' B) j G, W+ `8.10 Internal Chip ESD Damage 258) b2 Z% e2 F: a6 s
8.11 Stress Dependent ESD Behavior 263
! H1 b0 F/ G2 F8 M9 J; v; m& M( @8.12 Failure Mode Case Studies 267
8 `$ U8 Z( _. D& L x# |8.13 Summary 271( t: }5 y! S; @) S$ b. i# m
Bibliography 272
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