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8 Failure Modes, Reliability Issues, and Case Studies 228
( ~; {6 e5 N1 D5 P8.1 Introduction 228
' N- p5 U" V6 h+ p! D3 C8.2 Failure Mode Analysis 229
, w, i. z4 {; ]8.3 Reliability and Performance Considerations 238
9 H2 ?7 j/ y/ {8.4 Advanced CMOS Input Protection 2397 `: R5 Y- n6 ^
8.5 Optimizing the Input Protection Scheme 2428 j: M% `4 o1 g- [
8.6 Designs for Special Applications 249
7 K, s0 X1 v& t! x8.7 Process Effects on Input Protection Design 253- p+ L9 l* `; h, p$ H& A! E
8.8 Total IC Chip Protection 255
+ I9 j4 k! ]& }$ H1 }) h6 n8.9 Power Bus Protection 2561 u, l8 a3 S+ z: I$ U @
8.10 Internal Chip ESD Damage 258
' S( j8 {! M( Z$ r) n O8.11 Stress Dependent ESD Behavior 263
8 v; t `0 V( W, A8.12 Failure Mode Case Studies 267
- E4 P9 \# C' j+ M3 L4 Y8.13 Summary 271
7 f" x' f' v e7 j3 f% X# cBibliography 272- H! X4 o+ v5 k8 o
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