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8 Failure Modes, Reliability Issues, and Case Studies 2285 ]+ p( [* P' N1 \; p4 @7 v
8.1 Introduction 228
3 n1 ^$ j8 N( h" T8.2 Failure Mode Analysis 229/ F8 N) p. H! @8 {$ l- S
8.3 Reliability and Performance Considerations 238
; I1 N0 W& z" W$ i8 D8.4 Advanced CMOS Input Protection 239
1 V+ H j+ k$ w* H7 S5 y+ }7 x8.5 Optimizing the Input Protection Scheme 242
1 T3 H W k# t8.6 Designs for Special Applications 249" G- H, c( c! _8 ?+ X0 z2 I
8.7 Process Effects on Input Protection Design 253
3 f/ \2 N( j* J8.8 Total IC Chip Protection 255
8 ~- T" f& L- U8.9 Power Bus Protection 256
8 c9 f5 i: w. e4 M5 F, I8.10 Internal Chip ESD Damage 2583 f2 L3 a. z* F% ]# ]
8.11 Stress Dependent ESD Behavior 263
3 c6 g% Y' @0 ~, X7 e$ r9 \. b8.12 Failure Mode Case Studies 267
6 U8 X& C, j! s" _2 B9 d, E: q8.13 Summary 271
+ J1 ?4 B; p8 V+ {$ q5 `( O& PBibliography 272
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