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8 Failure Modes, Reliability Issues, and Case Studies 2281 x- v( [+ o- t8 ~: U
8.1 Introduction 2280 s* M; f' {6 i
8.2 Failure Mode Analysis 2290 `0 y! m+ F; h) i# c
8.3 Reliability and Performance Considerations 238
$ r; a8 n7 R, V3 I8.4 Advanced CMOS Input Protection 239* L) S) ?# v5 k7 Q, V# n" x/ \
8.5 Optimizing the Input Protection Scheme 242! j, h4 [- I U4 A. O; v* L
8.6 Designs for Special Applications 249' \: r- I' F+ x, B6 x& M
8.7 Process Effects on Input Protection Design 253
5 j" M5 S# |6 _8.8 Total IC Chip Protection 255
$ t U5 }2 h/ h$ y. s7 k& l( g8.9 Power Bus Protection 2560 P( i0 n0 Y _
8.10 Internal Chip ESD Damage 258# W9 }7 ]6 Q& j" y' C X8 A
8.11 Stress Dependent ESD Behavior 263
- L% l6 U8 q5 H: K: W0 q. C8.12 Failure Mode Case Studies 267: ], l% \8 R3 F) M
8.13 Summary 271; Y* u1 a( G9 K; V/ w
Bibliography 272
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