靜電放電測試

ritafung

剛剛研究了靜電放電（ HBM ＆ MM） JEDEC標準，實在需要很長的時間去進行測試。假設該IC具有數以百計的pin，很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試？

m851055

竹科閎康科技有此業務
電話在網頁就查的到了.......................

cuban487

很多實驗室好像都有,但都在台北.
儀特好像就有可以去查ㄧ下

kyyyyyykimo

目前新竹地區有"宜特"與"閎康"兩家比較大
  N+ `3 b' v& ?% z1 Z" g我的建議是去閎康，會比較適合。
5 ~6 |5 e# H# C/ D因為我本身工作性質也是有接觸到ESD測試
6 _+ w1 u# G5 I% T- C測試多Pin需要花費時間比較長久，可是你們HBM是使用JECDE
6 E! c0 s- x" r/ Z* [在Zap的次數明顯比軍歸來的少了。
) i$ m7 p" ?2 M$ I2 u

ritafung

my company is pursuading to MIL-Std ...
, }* L, H9 F8 X* ]actually any company need MIL-Std? Our application is not for military purpose....

wesleysungisme

For ESD test (HBM)
The following are the test combination:
( Q/ ^" r; K" j1. Power to Power
2. Power to Ground
3. IO to Power
4. Io to Ground
5. IO to IO
(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)

: e- X7 G- D) Xthe total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
7 [) C8 m! t( i" vFor example: You have IO1/IO2/IO3/P1/P2/G1
2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)
$ l! b1 x* N% k" k+ ]So for high pin count it will take a lot of time. But it won't take more than a week(for one chip).
( @  m5 p' W  B9 ~
* Y; V" x# n$ TFor your reference.

f5882077

樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢??
有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~

ritafung

thanks wesleysungisme for your answer.
as our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming.
! X+ J2 _- m8 \and there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.