靜電放電測試

ritafung

剛剛研究了靜電放電（ HBM ＆ MM） JEDEC標準，實在需要很長的時間去進行測試。假設該IC具有數以百計的pin，很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試？

m851055

竹科閎康科技有此業務
- o: i' F+ c/ `電話在網頁就查的到了.......................

cuban487

很多實驗室好像都有,但都在台北.
儀特好像就有可以去查ㄧ下

kyyyyyykimo

目前新竹地區有"宜特"與"閎康"兩家比較大
我的建議是去閎康，會比較適合。
" B. t# g' |6 `, j& M因為我本身工作性質也是有接觸到ESD測試
5 c6 Q( f& u4 L$ f5 n% C7 Q測試多Pin需要花費時間比較長久，可是你們HBM是使用JECDE
在Zap的次數明顯比軍歸來的少了。
  Q; g: z+ ?7 ^+ C( S& z

ritafung

my company is pursuading to MIL-Std ...
actually any company need MIL-Std? Our application is not for military purpose....

wesleysungisme

For ESD test (HBM)
The following are the test combination:
) ]3 e! S) `) L  U  K1. Power to Power
( @' V/ l- i1 F2 D7 C1 s2. Power to Ground
) t. z# q. a! V$ ?0 e* _( a3 I- \3. IO to Power
% a6 Q/ ?/ k( d8 G0 H+ i4. Io to Ground
* T  p3 n- u$ D. @$ B0 J" _5 J5. IO to IO
(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)

the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
* E& b8 `% C( |For example: You have IO1/IO2/IO3/P1/P2/G1
! I- Y  ?  q& z2 X) F1 L% J2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)
" {: m1 ]0 C* H/ LSo for high pin count it will take a lot of time. But it won't take more than a week(for one chip).

For your reference.

f5882077

樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢??
0 a0 d! H% s: D  q" |有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~

ritafung

thanks wesleysungisme for your answer.
as our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming.
6 V: G" Y" t1 R, f6 k  nand there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.