Chip123 科技應用創新平台

 找回密碼
 申請會員

QQ登錄

只需一步,快速開始

Login

用FB帳號登入

搜索
1 2 3 4
查看: 6503|回復: 7

[問題求助] 靜電放電測試

[複製鏈接]
發表於 2008-4-12 00:55:01 | 顯示全部樓層 |閱讀模式
剛剛研究了靜電放電( HBM & MM) JEDEC標準,實在需要很長的時間去進行測試。假設該IC具有數以百計的pin,很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試?
發表於 2008-4-12 08:07:37 | 顯示全部樓層
竹科閎康科技有此業務+ D/ T# N# a3 w) _9 S9 p
電話在網頁就查的到了.......................
發表於 2008-4-12 11:12:12 | 顯示全部樓層
很多實驗室好像都有,但都在台北.+ X% s1 _: K+ c8 |; d6 l
儀特好像就有可以去查ㄧ下
發表於 2008-4-16 13:02:11 | 顯示全部樓層

很多家實驗室都有啊

目前新竹地區有"宜特"與"閎康"兩家比較大
' |3 a7 p6 Y8 g! _) Q2 ^我的建議是去閎康,會比較適合。  {/ u2 D' a1 U% A( B8 F' v8 V& e
因為我本身工作性質也是有接觸到ESD測試8 h/ n, m* B) h8 e& g: h- g. n
測試多Pin需要花費時間比較長久,可是你們HBM是使用JECDE% Z+ y! |4 M2 O  X- P
在Zap的次數明顯比軍歸來的少了。
1 R/ ~3 S1 d8 z7 {* O0 T+ ~7 D) W
 樓主| 發表於 2008-4-22 00:07:49 | 顯示全部樓層
my company is pursuading to MIL-Std ...
: A( ^* q, g. c4 d4 l' uactually any company need MIL-Std? Our application is not for military purpose....
發表於 2008-5-21 12:14:35 | 顯示全部樓層
For ESD test (HBM)
8 q. R7 s4 ~) u; f% h, t6 TThe following are the test combination:4 x$ @$ h: |5 M' b7 q: f
1. Power to Power0 C8 z! ?+ s! b
2. Power to Ground
. k0 ~8 V. l* @, W3. IO to Power
# I! j+ |0 p2 z1 T4. Io to Ground  e) M0 q$ U+ J9 X6 h, f2 l* a
5. IO to IO  C, ]- D9 U% h% L5 F# P0 b- L
(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)8 p: P# c- O; d/ [3 J* d
. a0 Z# I/ u, O* h
the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG), _3 u* n5 w" {7 B/ P& [( f8 ?* c
For example: You have IO1/IO2/IO3/P1/P2/G1
9 F( x. K$ c1 B2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)
+ X' O, M' A' k5 }2 V6 z* MSo for high pin count it will take a lot of time. But it won't take more than a week(for one chip).
. l* c. T- _9 q( E# m* C  |
1 o* e/ r. @$ U9 g2 OFor your reference.
發表於 2008-5-23 15:02:54 | 顯示全部樓層
樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢??( ?8 g+ D* U& R+ ]( }
有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~
 樓主| 發表於 2008-5-26 21:15:09 | 顯示全部樓層
thanks wesleysungisme for your answer.
$ p, `% h+ N6 z1 P2 i$ Cas our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming.
( [  h) R4 f1 }$ Oand there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.
您需要登錄後才可以回帖 登錄 | 申請會員

本版積分規則

首頁|手機版|Chip123 科技應用創新平台 |新契機國際商機整合股份有限公司

GMT+8, 2024-6-23 07:10 AM , Processed in 0.121015 second(s), 18 queries .

Powered by Discuz! X3.2

© 2001-2013 Comsenz Inc.

快速回復 返回頂部 返回列表