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Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"% h3 i& _6 b* u8 d% X
An example for your reference...
8 R% Q: a- p: ~2 n' p6 P5 C
/ F& s2 ^! M) V& d! w----------------------------------------------------------------1 a" p" H9 l" A$ L4 f: ~7 q
***** Gate Capacitance Plots *****( }% j/ c: A! D" C
.lib 'your_component_model' lib_corner: G5 O8 c8 r. z# u7 ]
.temp operational_temp) e! }$ x8 x: T `" @% T; g2 @
.option dccap=1 post
7 J8 L" Q3 y3 u2 i) Q7 H' ]7 im1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
9 ?' l, D9 _/ k }: a$ c+ Pvd n_drain gnd 0
/ J$ e. U- f: k3 Vvg n_gate gnd 5
4 w6 ^4 {3 r" m1 avb n_bulk gnd 0$ t1 V$ u5 ]: u9 k
.dc vd 0 5.0 0.1
/ j7 ~4 ], f+ `) D.print CGG=lx18(m1)9 M" M+ l/ ?0 F4 }- ^: X9 a9 b+ u! J
+ CGD=par('-lx19(m1)')
* E" F7 c8 R% c+ CGS=par('-lx20(m1)'): T; Z6 y! ~ i5 L; ]
+ CDG=par('-lx32(m1)')% o& a( L9 ]8 M! J0 A' X
+ CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
# _# d' Y6 ?7 X. F& V& z+ CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
1 u Y U) n% ?& M+ \- V) B" H.ends
( ~& U3 ~7 ]& W$ O4 \! u& G
. s; V( C4 d8 E- }- C----------------------------------------------------------------$ S, ?1 k7 G6 M$ F! S9 a M
Six capacitance are reported in the operating point printout
) p% g( C x( ^ cd_total = dQD/dVD
; ^8 x. \3 s2 k0 h- }8 X1 u cg_total = dQG/dVG
9 E, J1 ]: W" B% d7 x# ] cs_total = dQS/dVS
4 ?, j& X* Z- A cb_total = dQB/dVB# c; G' e$ u* J
cgs = -dQG/dVS
3 ]; x; O5 _' ` cgd = -dQG/dVD; p5 G: Q/ T3 ]; w2 M% e4 A
There capcitances include gate-drain, gate-source, and gate-bulk
& x7 u! H- z9 X+ I3 b$ Y+ s- xoverlap capacitance, and drain-bulk and source-bulk diode capacitance.
@9 n4 M8 a) ?: X( ~! d, Y: p% t. s7 f' e0 @% L% C
CGG = dQg/dVG) M, ~/ n8 k9 U8 m% F4 M
CGD = -dQg/dVD; b( x x& _, ?9 B* T6 A
CDG = -dQD/dVG9 _' f9 q% E, Q$ H# w* E
+ [2 k! p, r4 x. W. Q7 {6 z3 o( P
The MOS element template printouts for gate capacitance are LX18~LX23
) O& U8 R! b. |, W5 x- Vand LX32~LX34.9 \) o8 Q, g- f/ D3 a% q2 K
) l* f; ^. \* J) T- ?, a* f
LX18(m) = dQG/dVGB = CGGBO
" {& P5 [9 d) l0 x5 G& j a( c: b0 rLX19(m) = dQG/dVDB = CGDBO
# Q7 J$ g, `+ @( Y+ vLX20(m) = dQG/dVSB = CGSBO
& P0 f! `+ G8 S2 W9 |9 y
4 \3 W; s3 F$ d. G' G! ~+ E( DLX21(m) = dQB/dVGB = CGGBO
" v( _! H9 j6 C* Y: MLX22(m) = dQB/dVDB = CGGBO
1 U) K, r& X5 ?6 j* Q ^' aLX23(m) = dQB/dVSB = CGGBO
; g5 m+ l+ A, W7 t. @: n7 K+ S; T8 ~, Q* a* n
LX32(m) = dQD/dVG = CDGBO
, D' W) g2 l$ _5 XLX33(m) = dQD/dVD = CDDBO- ?8 b* Y8 W9 e: h% Q
LX34(m) = dQD/dVS = CDSBO
' X& f( V( p$ B, Q) q
( M1 u" i/ _& |The equation shown above is for an NMOS with source-bulk grounded
7 w! M: m# v* `: L; H) C' ?configuration. Refer to the user's manual for more detail ^^ |
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