hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
2 B- }3 B1 l' B+ R/ v4 l3 H0 k8 x
要怎麼定義用
plot LX??
. ]! K: l5 d4 k
! Q* [( s6 C; q+ L請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
. Q% [: J7 l/ p! K6 P4 ]: C
7 Y1 ~0 X! M( A; I) D( lCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.
1 }; z* S' J: g0 w0 U" p- a9 r/ F

  \7 `$ Q" J' Z  T8 `6 V  C& XFor your reference.

0918429587

CAB_BS    LX28
CAB_BD   LX29

# D1 y* [: m5 _& \其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
2 S7 G' t. x" Q& L) m這是 CGDBO  CGSBO CBGBO

不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
An example for your reference...

----------------------------------------------------------------
# b9 o& C6 c5 D  @3 R; K0 G***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
% y& e$ Z4 ^( W.temp operational_temp
- H+ X& d( B  p& L! a2 D.option dccap=1 post
1 E$ o7 f- m% @+ em1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
- [* n# K& X6 z7 s! ^vd n_drain gnd 0
vg n_gate gnd 5
vb n_bulk gnd 0
.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
% S7 H4 L3 k2 d0 I% c( |( ]+        CGD=par('-lx19(m1)')
; B1 `! V9 o) V- H: Q0 b, H+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
& S( f( x, G. G.ends
; ~- @! z% S7 R9 e% c- _
----------------------------------------------------------------
% x' F; I7 ?3 f) GSix capacitance are reported in the operating point printout
    cd_total = dQD/dVD
- c! l  m1 R' h/ R( J' y, ~    cg_total = dQG/dVG
    cs_total = dQS/dVS
1 G$ j0 @& Q4 u$ G1 f    cb_total = dQB/dVB
9 h. o' ?5 r3 H0 u2 [    cgs = -dQG/dVS
' @8 E/ {( T% Q& W' \# D8 B    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
9 `+ z$ ?4 Q9 f$ m2 D$ Hoverlap capacitance, and drain-bulk and source-bulk diode capacitance.

" g; g5 w6 ~8 x: wCGG = dQg/dVG
, g0 x( n! @2 s) ~& N5 F1 H# `2 B) mCGD = -dQg/dVD
CDG = -dQD/dVG

The MOS element template printouts for gate capacitance are LX18~LX23
" d* X6 O2 R+ c. {+ D# Fand LX32~LX34.

LX18(m) = dQG/dVGB = CGGBO
" z6 i- ~7 G  YLX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO
! X+ D  b' V0 g6 U2 q0 U
LX21(m) = dQB/dVGB = CGGBO
$ i3 P. [6 P  t+ a% Z- wLX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO
' U% a- R; I: d5 Z) f9 {# r
LX32(m) = dQD/dVG = CDGBO
LX33(m) = dQD/dVD = CDDBO
* ]5 Z$ W0 ]/ b! d4 @, I& y9 SLX34(m) = dQD/dVS = CDSBO

The equation shown above is for an NMOS with source-bulk grounded
. L" H! C5 F) n/ L9 m, G7 J- `configuration. Refer to the user's manual for more detail ^^