hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
: L% i- U5 a2 q& D
要怎麼定義用
8 Q. r3 H# ~1 |; `  qplot LX??

請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
3 H& u+ F3 N; O. L( g3 L" J7 |7 i
% j! O& {) j9 v/ l- W1 i0 HCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.
) Q  J3 J* K) e; m+ e
& n! N) A* s1 d( o" U3 F) D
For your reference.

0918429587

CAB_BS    LX28
4 y7 B2 T+ ]) \9 m; [$ ?CAB_BD   LX29

其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
1 ^+ b# W$ a- ~8 Z/ \這是 CGDBO  CGSBO CBGBO

0 f. {- f( \7 J1 Z+ _! {8 W不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
# b" X- S4 P4 V* T6 MAn example for your reference...

----------------------------------------------------------------
***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
! ]; X- b. Z, @: [) }  L.temp operational_temp
.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
vg n_gate gnd 5
" O3 t1 e; n% I' q6 B: }vb n_bulk gnd 0
.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
* x& v! s* k9 X9 X: Y/ ?+        CGS=par('-lx20(m1)')
& I& V0 |: V& o+        CDG=par('-lx32(m1)')
8 F- j) M7 g7 E+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
; k! E! g* C. P+ D" g/ q+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends

& @$ t6 p  ~5 P( f% L# {----------------------------------------------------------------
Six capacitance are reported in the operating point printout
    cd_total = dQD/dVD
. u( X% }) }9 E1 X9 V$ L    cg_total = dQG/dVG
1 k  U1 S9 k6 r0 b% Y& {7 Y+ `    cs_total = dQS/dVS
2 R% k/ |! S7 r1 f+ E3 V; V. \  y$ u    cb_total = dQB/dVB
) H4 @5 I5 t! q8 R. r1 B' t9 E    cgs = -dQG/dVS
    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
% C. X" ^4 \6 p0 doverlap capacitance, and drain-bulk and source-bulk diode capacitance.

0 [# |- `% b7 o0 h' iCGG = dQg/dVG
# B2 Z+ [  p4 dCGD = -dQg/dVD
CDG = -dQD/dVG
$ ]/ S6 e7 {/ o7 R
The MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.
1 {& o. Z, X: [! |
LX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO

LX21(m) = dQB/dVGB = CGGBO
" z4 i, U+ A: }+ T& g( JLX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO

LX32(m) = dQD/dVG = CDGBO
# t9 d8 h  k: c" @' P) T: r7 P$ ^4 iLX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO

: K9 _- t2 n( |1 {4 ~( k8 G' |The equation shown above is for an NMOS with source-bulk grounded
1 l. _" k# S7 y9 o4 `configuration. Refer to the user's manual for more detail ^^