hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

要怎麼定義用
) E% V; ?5 ^  ]/ b. }4 Z( t1 qplot LX??

請各位幫忙一下

小朱仔

直接下.op及.probe
' F2 P, l' U( v# v4 F3 o' x* a找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
. J; S- x9 O1 x" Q
! I- A9 X' D- l) a6 ?* dCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.


For your reference.

0918429587

CAB_BS    LX28
( ]2 o1 A  s7 p9 a0 fCAB_BD   LX29
9 t4 l5 f3 ?* g
其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
# [! I' [: T  T1 v3 }這是 CGDBO  CGSBO CBGBO
4 K9 A: P& r; T% Y( k' g9 G
$ J  ~' O  U4 _* ^; F8 ^5 @不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
An example for your reference...
2 r& c, |" J2 \6 ?  V5 D! y
- f" r% |+ s7 B% K7 }% e- X! l----------------------------------------------------------------
***** Gate Capacitance Plots *****
2 V. r2 C+ ?& g2 e.lib 'your_component_model' lib_corner
.temp operational_temp
.option dccap=1 post
# q5 {8 k5 p; |' M$ ]+ X# @! nm1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
vg n_gate gnd 5
vb n_bulk gnd 0
.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
* }0 c) s. x7 ^( z/ E: R+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends

----------------------------------------------------------------
Six capacitance are reported in the operating point printout
) ^  e  O  @% h  M8 }" h/ }$ O5 w    cd_total = dQD/dVD
0 {" e  r, D7 y* w" t2 N    cg_total = dQG/dVG
    cs_total = dQS/dVS
4 L) D; Y+ _5 i# j% W$ }) O    cb_total = dQB/dVB
    cgs = -dQG/dVS
0 Z; S. G; W; J    cgd = -dQG/dVD
+ a& h; ?0 |* t7 O5 [! KThere capcitances include gate-drain, gate-source, and gate-bulk
- M8 w0 {3 s3 [6 X7 L4 `overlap capacitance, and drain-bulk and source-bulk diode capacitance.
1 w0 K- Y& L  O  O- d- W5 o- {
CGG = dQg/dVG
) S; s/ ?2 e) H; f2 ^0 qCGD = -dQg/dVD
$ f- }& V; m$ [7 w6 wCDG = -dQD/dVG
( J; i- d" I& y% c+ R) ~
# Q+ s. o0 M8 j/ i- iThe MOS element template printouts for gate capacitance are LX18~LX23
' h( v4 D8 y) F6 A1 Z  T8 U* Iand LX32~LX34.
+ v) c6 v5 s+ `- V1 t4 X3 r
0 U* a. U% B8 I0 E, {% DLX18(m) = dQG/dVGB = CGGBO
& @* H) O1 ]! S, GLX19(m) = dQG/dVDB = CGDBO
5 O$ x& \  }2 H& {; HLX20(m) = dQG/dVSB = CGSBO
7 Q' u! F/ ]" i
LX21(m) = dQB/dVGB = CGGBO
- N. I5 e( [7 x1 n( n) }7 S% M5 iLX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO

! @" \* T  a; X9 @9 y7 D5 SLX32(m) = dQD/dVG = CDGBO
LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO
3 I  r# R. ~6 l* R
8 N) x' r' m: aThe equation shown above is for an NMOS with source-bulk grounded
/ V* R) G' z% P8 C! a0 Sconfiguration. Refer to the user's manual for more detail ^^