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Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
4 F* q( E6 f! [' u6 N/ T( mAn example for your reference...7 y) p& K) @/ z+ R. ]. D
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8 L! Q7 m( u' G% a7 @' ? d% L) R+ T***** Gate Capacitance Plots *****( e/ Q5 L, ?( `( F
.lib 'your_component_model' lib_corner" J5 E2 I- _6 r& U3 X
.temp operational_temp! P, C# K+ n7 u6 v& V0 x
.option dccap=1 post: r3 w$ [" M) S
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-126 m8 [" b: l2 d D& u
vd n_drain gnd 0
1 |4 ~# a3 T2 p8 p& A! e n. Xvg n_gate gnd 5
( i( W& ~$ l: l5 lvb n_bulk gnd 0+ A2 A0 Z8 F6 D- _1 | P: ? \' d( X
.dc vd 0 5.0 0.1: b4 U4 E, `& L. k2 t$ ?- Z, k8 R6 A
.print CGG=lx18(m1)9 {+ ^( U9 C1 j" W- |. ]/ q6 ~, d
+ CGD=par('-lx19(m1)')) p, R5 T9 }8 e6 E. w' D7 D- O
+ CGS=par('-lx20(m1)'); A* ]# m& d5 ~( ]! m
+ CDG=par('-lx32(m1)')
% D9 ?& X* W8 \) `4 {9 g. b+ CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
$ o8 W6 P/ P7 U- ^3 D, J9 V2 {+ CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
S6 X' z, b4 A) G% n. D3 y2 B2 f4 a.ends
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2 S0 e, z% K7 P3 `0 p/ j3 ZSix capacitance are reported in the operating point printout6 `& ?0 t9 m, d. K% {
cd_total = dQD/dVD; e$ }. \# C1 ?- E( H+ M0 y
cg_total = dQG/dVG( T9 }* m* H _4 i! l; x
cs_total = dQS/dVS* S8 @9 g3 l% ?# w4 N+ u2 N
cb_total = dQB/dVB
3 R- A" f+ m& Y# j L cgs = -dQG/dVS
' [! I6 s4 c* R$ ?# o. x cgd = -dQG/dVD3 ?8 z, @) d/ P" ]- ^; y7 |8 r
There capcitances include gate-drain, gate-source, and gate-bulk
1 Q$ @! s9 N- W* @% uoverlap capacitance, and drain-bulk and source-bulk diode capacitance./ I. j2 g, k5 @: c+ Y
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CGG = dQg/dVG, e# X8 G* y0 l0 W2 k% z
CGD = -dQg/dVD8 ]9 {3 N6 l! z
CDG = -dQD/dVG5 d) v% W# ~+ e; a4 r( o* y
1 `/ b+ L3 e+ S% X R- ~! ?# s- XThe MOS element template printouts for gate capacitance are LX18~LX23
% m! q7 {' O4 f2 Y: Tand LX32~LX34.# i; k( X9 k+ _; r: I# M
, u$ r( r, }8 r) \" G. \LX18(m) = dQG/dVGB = CGGBO
1 C4 E) }: n, ~LX19(m) = dQG/dVDB = CGDBO
8 D5 H' d% J1 H7 A+ O- |9 T: QLX20(m) = dQG/dVSB = CGSBO
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LX21(m) = dQB/dVGB = CGGBO
* L1 y2 x, G/ U! X* [/ R% |! CLX22(m) = dQB/dVDB = CGGBO
: U' p' j0 E; z- `$ xLX23(m) = dQB/dVSB = CGGBO6 L' S. b4 a9 j3 [; d
- M7 s6 x, b8 h" W4 P: [LX32(m) = dQD/dVG = CDGBO
1 U% ~* t+ }3 B4 g2 [LX33(m) = dQD/dVD = CDDBO- U, j6 F5 D( b
LX34(m) = dQD/dVS = CDSBO1 y) f6 r6 A2 D# a. r/ b" X
+ K$ T0 b% v- ?, ?) Z4 O" \- N
The equation shown above is for an NMOS with source-bulk grounded
7 N8 {# V! `$ x: h4 [: d( u& hconfiguration. Refer to the user's manual for more detail ^^ |
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