hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

要怎麼定義用
plot LX??
5 S( \. f5 {1 N
請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.


For your reference.

0918429587

CAB_BS    LX28
CAB_BD   LX29

其他我找不到
# c! K& A4 [8 K" Q5 m0 b0 [: YCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
這是 CGDBO  CGSBO CBGBO

不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
  k3 f* D" F% Z4 QAn example for your reference...

----------------------------------------------------------------
: J7 q9 H3 o( f* z***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
- T5 R0 d. p0 Y% C.temp operational_temp
8 F# y9 G% e/ s: }3 T! k6 Q.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
, p; f% X' z9 k4 I- j% P; Cvg n_gate gnd 5
6 O) o/ \( Y. R$ z$ Fvb n_bulk gnd 0
.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
2 @" w9 S9 ^4 q$ O% ]! l4 S+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
8 X) D5 \* y# N4 I& M4 S.ends
( G# N3 q0 E% @4 g
----------------------------------------------------------------
3 B  e! w8 u' R+ g' X+ ?! kSix capacitance are reported in the operating point printout
& m) W" u& Q0 ^' v2 y9 _    cd_total = dQD/dVD
6 a8 t5 b2 n8 ]# p, J    cg_total = dQG/dVG
! z3 r* d# K2 y    cs_total = dQS/dVS
    cb_total = dQB/dVB
    cgs = -dQG/dVS
    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
1 e# }8 S8 Z; S$ l2 zoverlap capacitance, and drain-bulk and source-bulk diode capacitance.

& W$ w: K8 s: _7 e5 G( }CGG = dQg/dVG
) v% }- h& N( K& bCGD = -dQg/dVD
  w' V* X, U+ sCDG = -dQD/dVG
! L9 G1 X/ s+ L+ K  n
* E8 |* d- o1 k. S  z4 C# Y0 w7 n/ J: NThe MOS element template printouts for gate capacitance are LX18~LX23
1 s. J1 S0 j6 zand LX32~LX34.
5 H* z; f# v3 t$ X9 Y: L* B& W
! A1 b) D0 m1 S7 r- |2 wLX18(m) = dQG/dVGB = CGGBO
2 o+ E5 G, @/ l$ yLX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO
$ M; P+ X8 e, y# v" Z5 P, T
LX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO

7 }' F2 y; k; |8 j+ k& w; cLX32(m) = dQD/dVG = CDGBO
LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO

The equation shown above is for an NMOS with source-bulk grounded
configuration. Refer to the user's manual for more detail ^^