hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
9 ^  k1 q1 z/ {
要怎麼定義用
plot LX??
' {7 I8 X! c7 d0 C' P2 ^' ^! q" z* C
請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

. S) ^! t: e) f! B! HCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.

' M/ K  |. r1 b/ d. N2 A% k
For your reference.

0918429587

CAB_BS    LX28
CAB_BD   LX29
$ d3 L3 s  h: \; {# o" x
其他我找不到
7 _1 c& O- L, Z6 u: {; Y) _Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
) N% E# ~! b" W5 A這是 CGDBO  CGSBO CBGBO
# ]7 M! Q5 A# ]4 I8 K7 t
( u1 O5 l7 f' d( u不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
4 F* q( E6 f! [' u6 N/ T( mAn example for your reference...

----------------------------------------------------------------
8 L! Q7 m( u' G% a7 @' ?  d% L) R+ T***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
.temp operational_temp
.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
1 |4 ~# a3 T2 p8 p& A! e  n. Xvg n_gate gnd 5
( i( W& ~$ l: l5 lvb n_bulk gnd 0
.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
% D9 ?& X* W8 \) `4 {9 g. b+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
$ o8 W6 P/ P7 U- ^3 D, J9 V2 {+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
  S6 X' z, b4 A) G% n. D3 y2 B2 f4 a.ends
6 x6 l+ E/ m1 e- h' M
6 B7 O+ ~; @" v2 z$ j$ b* l8 ?----------------------------------------------------------------
2 S0 e, z% K7 P3 `0 p/ j3 ZSix capacitance are reported in the operating point printout
    cd_total = dQD/dVD
    cg_total = dQG/dVG
    cs_total = dQS/dVS
    cb_total = dQB/dVB
3 R- A" f+ m& Y# j  L    cgs = -dQG/dVS
' [! I6 s4 c* R$ ?# o. x    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
1 Q$ @! s9 N- W* @% uoverlap capacitance, and drain-bulk and source-bulk diode capacitance.

CGG = dQg/dVG
CGD = -dQg/dVD
CDG = -dQD/dVG

1 `/ b+ L3 e+ S% X  R- ~! ?# s- XThe MOS element template printouts for gate capacitance are LX18~LX23
% m! q7 {' O4 f2 Y: Tand LX32~LX34.

, u$ r( r, }8 r) \" G. \LX18(m) = dQG/dVGB = CGGBO
1 C4 E) }: n, ~LX19(m) = dQG/dVDB = CGDBO
8 D5 H' d% J1 H7 A+ O- |9 T: QLX20(m) = dQG/dVSB = CGSBO
9 Y# t9 M; W* G
LX21(m) = dQB/dVGB = CGGBO
* L1 y2 x, G/ U! X* [/ R% |! CLX22(m) = dQB/dVDB = CGGBO
: U' p' j0 E; z- `$ xLX23(m) = dQB/dVSB = CGGBO

- M7 s6 x, b8 h" W4 P: [LX32(m) = dQD/dVG = CDGBO
1 U% ~* t+ }3 B4 g2 [LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO

The equation shown above is for an NMOS with source-bulk grounded
7 N8 {# V! `$ x: h4 [: d( u& hconfiguration. Refer to the user's manual for more detail ^^