hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

# X3 |  I, B, B+ j要怎麼定義用
plot LX??
& \' b+ [$ \% C+ V
請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
' c- i5 o& Y  o9 X, e' M$ e3 }
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.

3 a; v3 I7 r7 H9 i; W5 b3 Z
' g/ T/ ~7 a. E6 F) x& gFor your reference.

0918429587

CAB_BS    LX28
5 A: Y, I8 c& B* n- u8 p& z) LCAB_BD   LX29

! ^9 R5 G3 o5 h* ]其他我找不到
4 q6 k! q( b/ S  ]# TCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
這是 CGDBO  CGSBO CBGBO

不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
: f% X9 z  E, m# {, U7 n8 v9 eAn example for your reference...
7 K0 S+ P" O9 A! ?9 \- H
----------------------------------------------------------------
***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
.temp operational_temp
.option dccap=1 post
# J" l; H9 h' W6 om1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
$ c! c7 w" O+ _6 E% y& hvg n_gate gnd 5
vb n_bulk gnd 0
# `0 x" T1 @3 e  b) R.dc vd 0 5.0 0.1
: j; i  a2 s3 J' e' H7 \: |.print   CGG=lx18(m1)
# {5 Z% m7 x0 s. o# V  F+        CGD=par('-lx19(m1)')
2 H: Q0 A) g, o* c( `+ r: P+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
8 T+ D* o& ?6 _+ ~- W. e. X7 `8 f# \& t+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
$ ~4 o2 C* d+ F  ?1 h6 Y.ends

----------------------------------------------------------------
  n. T1 H# T7 y9 vSix capacitance are reported in the operating point printout
, h5 Q( Y: N. W1 x3 ]3 A/ j* a* p    cd_total = dQD/dVD
; E; L3 q) w! \    cg_total = dQG/dVG
7 g2 Q, b2 W7 p$ f+ E' [" ?    cs_total = dQS/dVS
    cb_total = dQB/dVB
    cgs = -dQG/dVS
    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
overlap capacitance, and drain-bulk and source-bulk diode capacitance.
9 ?4 |  B2 g2 E/ S- j7 N
CGG = dQg/dVG
CGD = -dQg/dVD
CDG = -dQD/dVG
0 F0 M1 D( d5 x. E6 R. Y* z7 q6 x$ n
The MOS element template printouts for gate capacitance are LX18~LX23
8 I) y) e( o, T. M" m, wand LX32~LX34.
( g6 y: K* s& C
" N$ u8 y0 I+ p. y' W* D% p- \0 zLX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
1 {6 l2 R( \6 j& u8 K5 X3 VLX20(m) = dQG/dVSB = CGSBO
7 a( M3 }2 L6 [8 Z1 I' U0 I& X
: q4 Q3 q7 i5 C/ m7 P! d9 VLX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
0 p; Z" Q) ]) J% |" Y5 d, jLX23(m) = dQB/dVSB = CGGBO
, o5 A; w* U! N# n; M5 f( t
2 X2 a% x2 W$ h, ?* T, N  Z/ I+ sLX32(m) = dQD/dVG = CDGBO
LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO
7 h3 P7 L; g$ r' p0 {6 g
The equation shown above is for an NMOS with source-bulk grounded
& \- u3 b: J; I& q/ qconfiguration. Refer to the user's manual for more detail ^^