Modelsim的錯誤訊息

w10789173

我寫了一個testbench,但是透過modelsim來驗證結果,卻得到以下的錯誤訊息,請有經驗的人指點我一下,謝謝!
/ ]1 X' Y4 g, ~- v- j% s# Loading C:\FPGAdv72LS\Modeltech\win32/../ieee.std_logic_arith(body)
' u0 l( Z% Y3 k4 T# Loading C:\FPGAdv72LS\Modeltech\win32/../ieee.std_logic_unsigned(body)
# Loading work.tb_memory_64(behavioral)
# Loading work.memory_64(behavioral)
" |5 K) W0 N- K) R# ** Error: (vsim-3817) Formal port "clk_l" declared in the entity is not in the component.
#    Time: 0 ns  Iteration: 0  Region: /tb_memory_64/uut  File: C:/Documents and Settings/Simulation/®à­±/RAM64/memory_64.vhd
# ** Error: (vsim-3732) C:/Documents and Settings/Simulation/®à­±/RAM64/tb_memory_64.vhd(37): No default binding for component at 'uut'.
$ T9 \; o% ]. P+ h3 w#  (Port 'clr_l' is not on the entity.)
#         Region: /tb_memory_64/uut
# Loading work.mem_coldec(arch)
  P, Y" g5 g! I% R3 k- Y% K  C# Loading work.mem_rowdec(arch)
7 \4 D5 ~( J, ^+ ~# _) e+ ^# Loading work.mem_matrix(behavioral)
# Error loading design
7 s# t! r, h' c* m7 t+ D& [-----------------------不是很懂為何有這錯誤訊息!?