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我寫了一個testbench,但是透過modelsim來驗證結果,卻得到以下的錯誤訊息,請有經驗的人指點我一下,謝謝!
, I1 I0 b: W& f9 D1 E- Z# Loading C:\FPGAdv72LS\Modeltech\win32/../ieee.std_logic_arith(body)
1 m8 x0 G: Q& o8 ^# Loading C:\FPGAdv72LS\Modeltech\win32/../ieee.std_logic_unsigned(body)
: F. K- t* d2 z8 ~+ P4 ` q# Loading work.tb_memory_64(behavioral)2 G5 \0 u/ P7 T" @: t- O
# Loading work.memory_64(behavioral)
# C: T6 T& U2 \! P! _# ** Error: (vsim-3817) Formal port "clk_l" declared in the entity is not in the component./ v9 U0 u( E7 s, }
# Time: 0 ns Iteration: 0 Region: /tb_memory_64/uut File: C:/Documents and Settings/Simulation/®à­±/RAM64/memory_64.vhd. `* k1 S0 l$ F7 p& m0 W7 s# {0 [
# ** Error: (vsim-3732) C:/Documents and Settings/Simulation/®à­±/RAM64/tb_memory_64.vhd(37): No default binding for component at 'uut'., @8 N) |7 \; A' h6 b7 f; o
# (Port 'clr_l' is not on the entity.)8 B) b; @" F, _5 M) S, |
# Region: /tb_memory_64/uut
" n, s# p5 E, z) `- c" r# Loading work.mem_coldec(arch)
% S1 g i: k5 c6 I# Loading work.mem_rowdec(arch)
& ~) ]+ u S$ p: K Y# Loading work.mem_matrix(behavioral)
2 t+ E( X5 @ v$ ^# Error loading design
% j; U7 Z% Z! O6 V+ u3 z-----------------------不是很懂為何有這錯誤訊息!? |
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