|
我寫了一個testbench,但是透過modelsim來驗證結果,卻得到以下的錯誤訊息,請有經驗的人指點我一下,謝謝!
& b. z4 E4 [' n5 ^# Loading C:\FPGAdv72LS\Modeltech\win32/../ieee.std_logic_arith(body)
# ~' E3 b: F6 i' \# Loading C:\FPGAdv72LS\Modeltech\win32/../ieee.std_logic_unsigned(body)
3 i7 f5 b5 A) B# W4 r# Loading work.tb_memory_64(behavioral)
/ R [; }& `, J. l; c! [/ _# Loading work.memory_64(behavioral)
; y1 ~, p6 a, M+ ?" V N- y# ** Error: (vsim-3817) Formal port "clk_l" declared in the entity is not in the component.
2 ?7 U) h1 c/ n0 r% S0 @5 V( w0 p' |' V2 i# Time: 0 ns Iteration: 0 Region: /tb_memory_64/uut File: C:/Documents and Settings/Simulation/®à­±/RAM64/memory_64.vhd' H5 u- n; T5 D* s
# ** Error: (vsim-3732) C:/Documents and Settings/Simulation/®à­±/RAM64/tb_memory_64.vhd(37): No default binding for component at 'uut'.
3 p$ z3 q3 @ q# (Port 'clr_l' is not on the entity.)
: Q* Y) j6 Z! }# Region: /tb_memory_64/uut( M& q) K) A" B" a9 V9 @
# Loading work.mem_coldec(arch)* ]; Z( t% ~6 T6 f/ h* e+ X
# Loading work.mem_rowdec(arch)
; O ?0 b$ }- H0 G9 @9 @# Loading work.mem_matrix(behavioral)
( C0 y( s, p2 L7 C# Error loading design L) w# x/ V1 O. ~* o/ o0 U: x
-----------------------不是很懂為何有這錯誤訊息!? |
|