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徵求記憶體6-bit data in 64個字組,不過不要用陣列的方式,很感謝大家提共意見,不過都不是實際記憶體電路的VHDL,我想要的是一個column decoder,一個row decorder,使用port map latch 64個,輸出要使用三態閘,個人想法如下:
6 K( P- c+ t0 A: N8 g6 P4 DLIBRARY ieee;8 |) P" U( Y: `$ {( P7 |2 b
USE ieee.std_logic_1164.all;
0 S) c- A- e0 u* W7 Z" pUSE ieee.std_logic_arith.all;
3 {( T8 y% j) K+ S+ C: Z
] [3 b) c0 D( j& p BENTITY memory_64 IS G( o, \" g* \! ~; a) x
PORT(
$ `! {4 s' f) K' k; L mem_in : IN std_logic_vector ( 5 DOWNTO 0 );
& Z! R0 C! \" C. f mem_out : OUT std_logic_vector ( 5 DOWNTO 0 );$ E' I4 D8 S! D/ S( p
clr_l : IN std_logic;8 P2 V: D# [9 M+ S. h" I3 m* a
mem_addr : IN std_logic_vector ( 5 DOWNTO 0 )
1 B0 F) U9 r# [9 X! y );
- {& I& `4 g' r7 w0 R2 ?& `4 L) \6 K. Z' ^! X1 m+ H
-- Declarations, k' u6 R; W1 R
# {& m# } ~# L1 \2 z8 i' d' \END memory_64 ;! [- A0 `1 i4 o
* a% |7 R4 x3 l0 O9 L S6 O--2 v: y4 N4 I% s$ v5 v7 l8 a
ARCHITECTURE arch OF memory_64 IS" b) ^% m- @" u+ B' S9 e H" ]3 H
-- column decoder
. a) u+ s: e# s; `# ccomponent mem_coldec
* Q$ {9 L& E+ R. o& H% ^- y w# ~ PORT( ( g7 o5 q8 N8 {) J* h6 o& Y
col_addr : IN std_logic_vector ( 2 DOWNTO 0 );
, Z' }& u% }. ~7 L1 @0 U col_sel : OUT std_logic_vector ( 7 DOWNTO 0 )
6 p% l5 S0 L5 w6 L& y7 r );7 I! j/ `( o G
end component;
- x' T1 |& {. O-- row decoder
/ k* J1 d6 G$ f- R$ Y7 w% [' } C3 Dcomponent mem_rowdec2 `0 g0 ?+ Q1 P- G5 @( L
PORT(
' o, z# V0 H! s9 A! C, q+ S' i1 H row_addr : IN std_logic_vector ( 2 DOWNTO 0 );
: \2 Y+ ^8 j/ T* |8 Q M3 ] row_sel : OUT std_logic_vector ( 7 DOWNTO 0 )
! k( y) k. `8 \; J; N9 B/ _4 Z) H );: r2 e3 x3 q& l/ M
end component;
- f, V! q# D1 t% ~; u-- latch array ( ~4 v/ K T. y) J) V P$ ?! R& K
component latch_cell5 n2 D: C4 U& w+ ^/ M
PORT(
6 E" s( V* C1 K! N1 B! d( Y n8 [ clr_l : IN std_logic;; W1 l5 T# B G* x7 C
col_sel : IN std_logic;! B7 E) U& I6 C' ?) i) T/ [
row_sel : IN std_logic; * C2 I2 i! y! ?7 C* D! i( O
data_in : IN std_logic_vector ( 5 DOWNTO 0 );8 Z* ^7 I5 e$ n" e
data_out : OUT std_logic_vector ( 5 DOWNTO 0 )$ |# l3 f1 ~, p
);: g9 F3 ?( a+ V, _. t) S/ o
end component;
1 u1 m+ }4 Q) `* w1 q; D" X3 N7 ~. j$ b/ w
signal smem_out : std_logic_vector ( 5 downto 0 );
' i2 d, r' Q1 W0 E$ ~* Asignal scol_sel,srow_sel : std_logic_vector( 7 downto 0 );
/ C, Z. f. W- n. \/ F* l9 w1 ^' zBEGIN% y1 H* I$ [. j
u_0 : mem_coldec port map(mem_addr( 5 downto 3 ),scol_sel);0 Z w8 g0 `3 H
u_1 : mem_rowdec port map(mem_addr( 2 downto 0 ),srow_sel);
5 b+ C/ v7 I1 x7 l6 g7 Y g0 : for i in 7 downto 0 generate -- column generate3 q* _8 m N( @) h' O* ?& J4 Z
g1 : for j in 7 downto 0 generate -- row generate
' S8 I& d% C0 b/ C# G u_2 : latch_cell2 y' i! O/ _ H8 c3 y" U$ T2 g
port map(
% _7 u2 k# h1 u+ {$ T" }7 h9 q col_sel => col_sel(j),1 d- N% D9 P0 ?. K: ]7 S
row_sel => srow_sel(i),
- o+ T# T" _4 a- U data_in => mem_in,0 Q5 E+ U8 y- g7 y
data_out => mem_out(i); f7 X4 l+ y n7 [ j
);
- @ O. v d& ?- K3 J7 Q end generate;
9 l, u9 E7 A o4 D$ a: U6 e end generate;
% L) a9 _4 h0 ]5 }5 C3 \3 I- b1 u1 B: FEND ARCHITECTURE arch;
, P; a- x l! b不過模擬很久,始終沒辦法寫進我想要寫的位址,試寫了很久,但是始終寫不出來,所以請大家幫個忙,不然那些範例網路上都有,有點急,請大家廣發建議,感謝大家! |
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