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徵求記憶體6-bit data in 64個字組,不過不要用陣列的方式,很感謝大家提共意見,不過都不是實際記憶體電路的VHDL,我想要的是一個column decoder,一個row decorder,使用port map latch 64個,輸出要使用三態閘,個人想法如下:
$ \& W8 O% a( X# E5 |" \4 rLIBRARY ieee;
' `5 J3 A# O- b, t# v4 |USE ieee.std_logic_1164.all;# R6 Q, z+ a: l1 i; c: D% c' D
USE ieee.std_logic_arith.all;2 P! T) J1 E7 |& q0 Q
' x# S0 w; K5 s6 t8 Q# q9 ZENTITY memory_64 IS! ?- J) c2 m, z; S% [1 [% r
PORT(
+ F) Y7 v0 _8 F* d R: t3 D6 f: q mem_in : IN std_logic_vector ( 5 DOWNTO 0 );
7 ?- A- A& f6 Y* T/ b mem_out : OUT std_logic_vector ( 5 DOWNTO 0 );; L" }9 `1 G. Z" w7 t1 D" |
clr_l : IN std_logic;
3 H j I" v) F1 p! v mem_addr : IN std_logic_vector ( 5 DOWNTO 0 )8 X0 k8 N6 m$ ^- m( A1 s9 Y% ]
);
: [+ {! t, h6 ~7 R! |3 `& O1 ~" K2 o
-- Declarations! R7 l1 l- {! s# G. e a, J
! K4 Q' g+ u1 j7 H7 _; M& f; h; U; iEND memory_64 ;1 A. W6 t& U6 {' i/ F
% i8 f, I. H+ I8 R5 v" p
--
; n# b4 N7 q) qARCHITECTURE arch OF memory_64 IS
! I/ ^. H6 O$ }$ k5 E-- column decoder9 Z5 r5 u, Q9 {' l9 w; T$ K7 T6 ^
component mem_coldec
6 z4 ]8 w" W( H4 \, y" I, X& N PORT(
1 o A: x& M& G1 o9 a4 [ col_addr : IN std_logic_vector ( 2 DOWNTO 0 );
, R) _) {# Y3 ]0 Z col_sel : OUT std_logic_vector ( 7 DOWNTO 0 ): F( j7 u8 ~" U( ?
);
3 h$ P; M& @- G! ]" A* T5 ~end component;
5 }. G+ r1 [) c2 \-- row decoder
, i6 d3 ~/ ]$ C+ s; V! Ucomponent mem_rowdec2 {6 C1 q+ I @9 \
PORT( ' b9 _# E" d6 x( d- q; l( p6 T
row_addr : IN std_logic_vector ( 2 DOWNTO 0 );
: t* l+ T. g, q% N# _. D- { row_sel : OUT std_logic_vector ( 7 DOWNTO 0 )
$ t1 L- M; v* e: s );6 X" }& [ ?6 z$ ]
end component;
. ~1 s5 m* o8 Y0 f0 M! U+ o( G-- latch array / C# S1 ]2 G3 p% [5 v
component latch_cell
1 E6 r; ^! r, L& p7 h; F PORT( " M- T( Y9 V0 R% |8 X+ }, w" ^
clr_l : IN std_logic;0 q7 C8 r6 F9 o7 g* \
col_sel : IN std_logic;
0 b& u* J+ L: e. T row_sel : IN std_logic;
9 o a# g7 N6 q7 N data_in : IN std_logic_vector ( 5 DOWNTO 0 );
; c9 B" z! {4 r0 J" o0 `& u data_out : OUT std_logic_vector ( 5 DOWNTO 0 )
, N# W+ Z; G5 K b: b; P, T! n );9 m+ l8 f/ c/ A6 B
end component; % @- l$ O: P* m/ Y/ Q; P: i
5 K. F4 l; `& W7 L8 Csignal smem_out : std_logic_vector ( 5 downto 0 );) c, o# D s' n+ V2 X. q# v& C9 a
signal scol_sel,srow_sel : std_logic_vector( 7 downto 0 );
* h H; l/ H9 R1 o" z0 P3 Z4 qBEGIN
% Q7 b A2 i: ]% Z u_0 : mem_coldec port map(mem_addr( 5 downto 3 ),scol_sel);
6 `8 Y# }. o0 W% F9 }7 W# C u_1 : mem_rowdec port map(mem_addr( 2 downto 0 ),srow_sel);
6 ~2 e7 J' J( x4 Q Z8 p g0 : for i in 7 downto 0 generate -- column generate: I$ ?# u0 x: |' S
g1 : for j in 7 downto 0 generate -- row generate! Z+ I+ X: l! h) C* i6 S9 A
u_2 : latch_cell4 v7 T0 f/ }% [8 g
port map(
7 v. F& o7 x0 y col_sel => col_sel(j),
1 }( R6 k) k* J2 v row_sel => srow_sel(i),: y' I- Q9 p$ N1 V- j
data_in => mem_in,. H5 {! H T- m
data_out => mem_out(i)9 t% c7 N5 a- q
);
9 ~% X$ P- H$ [' W D1 a end generate; + P3 A& Q0 [" }+ e. M
end generate;4 n* Z" d9 q. B9 ]: O
END ARCHITECTURE arch;
: b6 T2 } _; `5 t& J不過模擬很久,始終沒辦法寫進我想要寫的位址,試寫了很久,但是始終寫不出來,所以請大家幫個忙,不然那些範例網路上都有,有點急,請大家廣發建議,感謝大家! |
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