記憶體問題

w10789173 · 發表於 2008-3-7 06:34:59

各位VHDL高手們,小弟寫了個6 X 64的記憶體,不過我試用實際的硬體電路來思考,並非使用軟體陣列的方式,如下:
我設計了一個decoder for column address selection,一個decoder for row address selection,然後使用generate產生64個latch陣列,但是現在我不知道該如何指定我的腳位,懇請各位給點意見,謝謝!

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY memory_64 IS
PORT(
   mem_in : IN    std_logic_vector ( 5 DOWNTO 0 );
   mem_out  : OUT std_logic_vector ( 5 DOWNTO 0 );
   clr_l : IN    std_logic;
   mem_addr : IN    std_logic_vector ( 5 DOWNTO 0 )
);

-- Declarations

END memory_64 ;

--
ARCHITECTURE arch OF memory_64 IS
-- column decoder
component mem_coldec
PORT(
   col_addr : IN    std_logic_vector ( 2 DOWNTO 0 );
   col_sel  : OUT std_logic_vector ( 7 DOWNTO 0 )
);
end component;
-- row decoder
component mem_rowdec
PORT(
   row_addr : IN    std_logic_vector ( 2 DOWNTO 0 );
   row_sel  : OUT std_logic_vector ( 7 DOWNTO 0 )
);
end component;
-- latch array
component latch_cell
   PORT(
      clr_l : IN    std_logic;
      col_sel  : IN    std_logic;
      row_sel  : IN    std_logic;
      data_in  : IN    std_logic_vector ( 5 DOWNTO 0 );
      data_out : OUT std_logic_vector ( 5 DOWNTO 0 )
   );
end component;

signal smem_out : std_logic_vector ( 5 downto 0 );
signal scol_sel,srow_sel : std_logic_vector( 7 downto 0 );
BEGIN
  u_0 : mem_coldec port map(mem_addr( 5 downto 3 ),scol_sel);
  u_1 : mem_rowdec port map(mem_addr( 2 downto 0 ),srow_sel);
  g0 : for i in 0 to 7 generate -- column generate
g1 : for j in 0 to 7 generate -- row generate
      u_2 : latch_cell port map(clr_l,scol_sel(j),srow_sel(i),mem_in,smem_out);
end generate;
  end generate;
END ARCHITECTURE arch;

w10789173 · 發表於 2008-3-7 12:30:16

不行耶,這樣就好了,我就是要講將實際的RAM電路寫成VHDL,不過還是感謝你的提示,難道真的沒有人這樣子做過嗎?

w10789173 · 發表於 2008-3-12 23:02:03

我只是試著把FPGA規劃成一顆RAM

沒有什麼特別的啦^^...

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