verilog clock generator question

jyunwei

Hi
# {1 R. M2 y" T% N9 i5 q5 v1 M$ l: H
  N6 |+ M" p: b) z8 l; f6 z. ^9 R) ~My clock generator is as follow
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; W1 u7 C, i" r! d# Q7 s1 o4 R4 j`timescale 1ns/10ps
4 y' m) [! C& ?  X% K" Q3 K7 l1 ~5 s
`define period 15
) |% r' ^1 b+ A0 a8 \, q
, Z) Y8 {: v% `module test();
, a& A" X+ y4 v0 yreg clk;

% Z$ n, y$ g& O. ^  g( |initial begin
6 ?. A& P8 C6 g" {( v7 J6 _clk = 0;
1 w+ B7 Q; p' v( u7 f  P" rforever #(`period/2) clk = ~clk;
end


But i check the waveform the clock period is always 14ns.
9 T8 G3 A! Y/ ?
Could anyone help me the question ?

8 X! L& }7 u6 M. a2 x' |Thanks

1 \1 j: v7 Y+ Y9 [) {* C2 l% W3 uendmodule