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Senior Physical Design Engineer* a% u2 y: b" [% Y7 T4 v. B; L
公 司:A famous IC company
6 n- `/ b ^7 J1 w% J5 s工作地点:南京
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0 Z# S+ g/ k e3 r9 G0 [Key Responsibilities
; X- Z D& P' ]3 I- eDepending on experience, key responsibilities will involve some of the following:
' F; d2 K& l2 K0 ^0 bIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
' A- \+ a# i+ F4 ZAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed. # a2 {: z a. S8 C9 W( B
Leading a team of physical design engineers and resolving the technical related issues. ( n4 t, g- p1 q8 q! z; x( S8 x
Crosstalk analysis, power analysis, and static timing analysis.
! }+ X- J# W6 A/ kWrite scripts in Tcl to improve productivity.
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Experience: 5+ years in physical implementation engineering
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Essential skills - R1 x7 H6 m. O% F' |/ Y
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills
0 e$ `) y" z; O+ cExperience with Magma or Synopsys place-and-route tool set and physical design project implementation. + X. P8 g, s2 S$ @0 Z6 o) Q, D/ q
Good programming skill. Capable of writing Tcl or Perl.
8 s& t s# s! sFamiliar with synthesis, static timing analysis. - J+ j& m( u- e( j
Self-motivated team worker, good verbal and written communication skills in English. \, e5 x0 M7 G% [) ?# G# k6 s3 [
Technical and team leadership proffered. Previous management experience highly desired.
0 o: Z4 x8 x; f* l1 mExperience with synthesis, DFT, and verification is preferred. |
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