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Senior Physical Design Engineer
' |' X+ J) Z6 n6 n" D* V7 _4 N9 o" T" j公 司:A famous IC company
( Z* q) e3 N0 v: t) o, I* E工作地点:南京, U! L+ l E3 f- E! N. D& [0 G
! Y4 U: K1 @: W& I0 `# w9 `5 `* p% _Key Responsibilities 8 }" B, d$ x3 e6 N2 S
Depending on experience, key responsibilities will involve some of the following: + U- W$ u A. I$ Q+ ^, u
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
, D$ F: o) J; _5 |' E/ `; A' DAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
: C- X! C+ u( P- Y$ H5 T7 q3 yLeading a team of physical design engineers and resolving the technical related issues. " s% O) {8 }( q7 `/ O+ t( l' f
Crosstalk analysis, power analysis, and static timing analysis. 9 t$ E) W) ^$ V
Write scripts in Tcl to improve productivity. ( e% e9 w. ?5 J, K! P; A
0 z |. ~2 d# `2 w
Experience: 5+ years in physical implementation engineering [8 y- q+ r+ C6 o6 m0 [
8 B6 E+ x" F; }' e3 aEssential skills # y: B3 E( J6 |& Q. ]5 S4 Q
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills ' F, R7 J J+ V7 v! x$ z
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation. % q6 {4 T& t" |/ Q/ X, r3 ^
Good programming skill. Capable of writing Tcl or Perl. 2 Q' ?! ~# E! k
Familiar with synthesis, static timing analysis. , ^4 d" ?3 i- f- A1 C
Self-motivated team worker, good verbal and written communication skills in English.
h) _7 W) N# ?; k+ eTechnical and team leadership proffered. Previous management experience highly desired.
; x4 P3 A% Y: F5 K, [9 RExperience with synthesis, DFT, and verification is preferred. |
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