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Senior Physical Design Engineer
1 l/ G/ l6 Q% u; n$ W- N公 司:A famous IC company' X5 L. x" X( \
工作地点:南京- C6 ^4 k) ^) S* [; p0 `
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Key Responsibilities 7 W$ _; T/ J/ W, g) k, F4 t2 Y& Y
Depending on experience, key responsibilities will involve some of the following: 6 l' r! R/ }( ]$ ~/ I& G( E4 G: _
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. ; q) f; z. t; b. r! |( N! y
As a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
. ^1 i* D& C* K7 \, XLeading a team of physical design engineers and resolving the technical related issues.
& l: ` B! Q3 I8 K; |Crosstalk analysis, power analysis, and static timing analysis. . y! v: X$ P1 D* ` _- T' h
Write scripts in Tcl to improve productivity.
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Experience: 5+ years in physical implementation engineering
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Essential skills t# n' Z' G6 D/ @, _
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills
: d; `# Q- L0 u- ]( B, j! w5 `: _Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.
1 n7 P2 [3 m$ m% M: I+ PGood programming skill. Capable of writing Tcl or Perl.
K: F* f) j" [# \. L/ _, VFamiliar with synthesis, static timing analysis. % Y$ m2 S) j) q5 `0 l
Self-motivated team worker, good verbal and written communication skills in English. & Z) }& O7 C4 z7 l$ q V
Technical and team leadership proffered. Previous management experience highly desired. ! F5 V) P5 A" ~2 a3 \
Experience with synthesis, DFT, and verification is preferred. |
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