|
FPGA and ASIC prototyping of Signal Processing algorithms with MATLAB and Simulink) J4 N9 q! ^0 e& B
Frank Liu, Communications and Semiconductor Industry Marketing, MathWorks Inc. 26p0 N6 G- w: w* ?" E
2 o9 T! r- I* K& V4 m' J/ tWhat You Will See In This Session$ E, f* E) U* l" `8 I0 v5 z
6 x L. L7 g- j
Introduction to Model Based Design For FPGA and ASIC% r6 ?1 z5 T! l7 k* }; K
Case Study – Audio Equalizer; ]; j6 I# o4 \6 j/ Q0 K- Y
Fixed-Point Modeling
' K5 `$ K5 l3 |HDL Code Generation5 k/ W! k; z1 j0 C9 P
Optimizing For Speed And Area3 P8 T+ w: Y D
Verification: HDL Co-simulation And FPGA-in-the-Loop
& f. f9 ]7 r1 t* @0 p, P4 ASummary And Next Steps' k. T. N1 o. q' `. [; O' ]
& m+ s- b8 p3 T) f1 l! V: @, E
" ]) N. G: I( K, `5 [% }
' Z. e9 \* P z; a7 e Y |
本帖子中包含更多資源
您需要 登錄 才可以下載或查看,沒有帳號?申請會員
x
|