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實驗平台~6 |( v8 m0 y; x5 ]
「Terasic」Altera DE0 多媒體開發平台,Cyclone III 3C16 FPGA+ q* [' e" P' @; ]0 c$ u% x! i3 C
在建構的過程中(僅放入cpu跟memory ip)
/ H5 ~5 I c3 }& |8 U& Y8 {0 Y3 Cno reset vector has been specified for this CPU7 u2 K) z& `. o
no exception vector has been specified for this CPU7 v3 g) i- e% G
這兩個訊息,沒辦法完全消除,這兩個一定要消除嗎
) o, ^, ^6 g* W) C* K5 ?0 G7 s5 Z) M試過
& D! ^; g/ H& R8 N' \on chip memory
' a/ Q: X/ f( Gsdram
; l2 x9 o3 h" w% p7 A3 c2 v9 b4 W5 `用上面兩個去試過所有可能的組合(mem/mem,sd/sd,sd/mem,mem/sd)
9 s5 ]) ?1 X* X: w: E( ~no reset vector has been specified for this CPU6 [* M1 }/ t( K' L6 p, ]* P. D: |! k
no exception vector has been specified for this CPU
8 T, J1 o* p# f+ L2 [5 }總是會有一個沒辦法去除(先選的訊息會被消除)' t( f6 n- n4 e+ ?" y% r: {$ L
" ]- O& L+ m% s/ Y2 v有人有在玩10.1版嗎?請多多幫忙~~" a6 ^! k) Z3 n& T* `' f, }
9 o3 n) G9 b# F. o4 w& p, x
目前打算~改用10.0sp1跟9.1sp2試試看) \* y$ u) H: U1 D) h; o1 L
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