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實驗平台~
7 }6 ?4 {7 [5 D9 i5 m4 d; n. I「Terasic」Altera DE0 多媒體開發平台,Cyclone III 3C16 FPGA
7 h0 k: Q7 [0 J' x$ C+ T在建構的過程中(僅放入cpu跟memory ip)
, R8 Q- Y9 P* O' R8 Nno reset vector has been specified for this CPU. i: k& d. Z8 C7 ?5 h6 g- W* _& p
no exception vector has been specified for this CPU' S. Y! l0 q: L+ }/ f
這兩個訊息,沒辦法完全消除,這兩個一定要消除嗎( X3 ]: v; H& K# a. G
試過
8 E. W# d# {: ]; T8 Pon chip memory! f: N. s& r) p9 \) Q
sdram
6 }. p$ E6 [/ k! B( n用上面兩個去試過所有可能的組合(mem/mem,sd/sd,sd/mem,mem/sd)1 |& n) }7 o/ `' A% p) f
no reset vector has been specified for this CPU
z; r i }$ _- Vno exception vector has been specified for this CPU
" F& z5 W9 Y/ F, R8 J4 F1 i總是會有一個沒辦法去除(先選的訊息會被消除)# X6 N. p6 z# y6 V( f
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有人有在玩10.1版嗎?請多多幫忙~~
r8 v0 O: D3 Q. Y6 Q" H4 b
5 d6 r4 z4 J1 F& a3 H目前打算~改用10.0sp1跟9.1sp2試試看* R5 Q8 y+ I( A. u3 O$ _
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