Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
  {. }- o* M1 v% b, N! V
Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

. l; E* }1 O2 f0 e0 f7 J6 f+ vAbstract—The n-channel lateral double-diffused metal–oxide–
semiconductor (nLDMOS) devices in high-voltage (HV) technologies
are known to have poor electrostatic discharge (ESD)
robustness. To improve the ESD robustness of nLDMOS, a co-design
  |, `: k5 q2 H5 q, zmethod combining a new waffle layout structure and a trigger
circuit is proposed to fulfill the body current injection technique
5 U0 s: h, [3 l- Uin this work. The proposed layout and circuit co-design method
! i1 J3 C& \' l  d3 v3 ^6 l# Ton HV nLDMOS has successfully been verified in a 0.5- m 16-V
3 `3 M! s- G; K$ R/ F' x% M8 S$ ibipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
  I9 `" I- K* ~process without using additional process modification. Experimental
- |- B) E  o9 z; M* I5 eresults through transmission line pulse measurement
# r+ v2 D: C- x, n: Kand failure analyses have shown that the proposed body current
injection technique can significantly improve the ESD robustness
of HV nLDMOS.

( S. u0 }8 M  |) g% jIndex Terms—Bipolar-CMOS-DMOS (BCD) process, body
" L" G- c" W$ O! q, v5 c1 jcurrent injection, electrostatic discharge (ESD), lateral double-diffused
5 P$ q5 _9 }  R7 Kmetal–oxide–semiconductor (LDMOS).

xp212125o

看起來有幫助
感謝分享
先下載來看看
thank you ~