Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj · 發表於 2010-7-3 10:06:20

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process

Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

Abstract—The n-channel lateral double-diffused metal–oxide–
semiconductor (nLDMOS) devices in high-voltage (HV) technologies
are known to have poor electrostatic discharge (ESD)
robustness. To improve the ESD robustness of nLDMOS, a co-design
method combining a new waffle layout structure and a trigger
circuit is proposed to fulfill the body current injection technique
in this work. The proposed layout and circuit co-design method
on HV nLDMOS has successfully been verified in a 0.5- m 16-V
bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
process without using additional process modification. Experimental
results through transmission line pulse measurement
and failure analyses have shown that the proposed body current
injection technique can significantly improve the ESD robustness
of HV nLDMOS.

Index Terms—Bipolar-CMOS-DMOS (BCD) process, body
current injection, electrostatic discharge (ESD), lateral double-diffused
metal–oxide–semiconductor (LDMOS).

xp212125o · 發表於 2010-7-28 13:46:05

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Circuit and Layout Co-Design for ESD Protection in BCD

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